Network Switch Egress Memory Allocation for Scalable Port Density
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Solution Overview
Problem
Existing network switches face challenges in efficiently processing data packets due to increased complexity and cost as the number of ports grows, leading to processing delays and scalability issues without significant increases in complexity or cost.
Innovation Solution
Implementing per-queue, circular egress buffers with large-scale memory units that allocate memory dynamically based on packet traffic, using relatively inexpensive DRAM external to the integrated circuit, and optimizing memory allocation and deallocation techniques to reduce processing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of ports on a switch is increased to accommodate more paths and traffic, then the switch can handle more network connections, but the complexity and cost of the switch increase significantly
Solution Approach 1:
The patent segments the switch architecture into multiple functional stages (ingress stage, classification stage, queuing stage, egress stage) that can independently process packets. This segmentation allows the switch to scale to more ports by adding parallel processing paths at each stage rather than increasing overall system complexity linearly
Solution Approach 2:
The patent introduces a multi-dimensional processing architecture where packets are handled across multiple stages and queues rather than a single linear path. By organizing memory into multiple queues and using staged processing, the system achieves high port counts through dimensional expansion of the data flow architecture
2Adaptability or versatility
If the number of ports on a switch is increased to accommodate more paths and traffic, then the switch can handle more network connections, but processing delays within the switch increase
Solution Approach 1:
The patent performs classification and queue assignment at the ingress stage before packets enter the queuing memory. By pre-classifying packets and determining their destination queues early in the processing pipeline, the switch eliminates later lookup delays and enables parallel processing paths, thereby reducing overall processing time even as port counts increase
Solution Approach 2:
The patent implements a pipelined architecture where multiple packets are processed simultaneously at different stages of the switch. While one packet is being forwarded, another is being classified, and a third is being queued, ensuring continuous useful action throughout the system and minimizing idle time and processing delays
3Quantity of substance
If traditional memory allocation methods are used for packet buffering, then memory can be allocated to store packets, but the frequent allocation and deallocation events increase processing delays
Solution Approach 1:
The patent merges multiple small packet buffers into larger queue structures that are pre-allocated in memory. Instead of allocating individual buffers for each packet, the system allocates contiguous memory regions for each queue and uses pointers to track packet positions, dramatically reducing the number of allocation and deallocation operations required
Solution Approach 2:
The patent pre-allocates memory regions for each egress queue before packets arrive. This preliminary allocation eliminates the need for dynamic memory allocation during packet processing, as all memory resources are reserved in advance and packets are simply placed into pre-designated memory locations within their destination queues
Data Source
AI summary
A network switch allocates large-scale memory units as data packets are received in order to implement per-queue, circular egress buffers. Each large-scale memory unit is larger than the maximum packet length of the received packets and is capable of storing a plurality of data packets, thereby reducing the number of memory allocation events that are required to process a given number of data packets. Efficient techniques for writing to and reading from the large-scale egress memory units have been developed and may be used to reduce processing delays. Such techniques are compatible with relatively inexpensive memory devices, such as dynamic random access memory (DRAM), that may be separate from the circuitry used to process the data packets. The described architectures are easily scalable so that that a large number of ports (e.g., thousands) may be implemented at a relatively low cost and complexity without introducing significant processing delays.