Switch Element Memory Cell Low Voltage Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile memory technologies face challenges with high voltage requirements, leading to reduced memory density, increased cost, and reliability issues, particularly in smaller semiconductor geometries, due to the need for large current to program or erase memory cells, which results in larger cell sizes and reduced performance.
Innovation Solution
A memory system is developed using a switch element connected to a JFET, where the switch element can be turned on with low programming current and off with high erasing current, allowing for improved memory density, reduced power consumption, and lower costs, with voltage and current requirements that scale with smaller semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is used to program NAND memory, then data can be stored in floating gate, but memory density is reduced and reliability deteriorates in smaller semiconductor geometries
Solution Approach 1:
The patent changes the voltage parameter from high voltage (15-18V) to low voltage (5V or lower) operation by switching from Fowler-Nordheim tunneling to charge trapping mechanism in ONO structure, making the memory compatible with smaller semiconductor geometries while maintaining reliability
Solution Approach 2:
The patent replaces the Fowler-Nordheim tunneling mechanism with a charge trapping mechanism using oxygen vacancies in the oxide layer, eliminating the need for high voltage and associated reliability issues in scaled geometries
2Productivity
If large current is used to program or erase MIM switch cell, then data can be written, but cell size increases and memory density is reduced
Solution Approach 1:
The patent changes the current parameter from high current (100 μA) to low current (10 μA or lower) operation by using a different switching mechanism that relies on voltage-controlled charge trapping rather than current-driven phase change or resistance switching, thereby reducing cell size and increasing memory density
3Quantity of substance
If series connection configuration is used in NAND memory, then data storage capability is improved, but fast random access performance is degraded
Solution Approach 1:
The patent segments the memory into independently addressable blocks with parallel access capability, allowing different blocks to be accessed simultaneously while maintaining high storage capacity, thus resolving the trade-off between capacity and access speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory density, lowers power consumption, increases reliability, and reduces costs by enabling efficient programming and erasing with lower voltage and current levels, while maintaining performance for fast random access needed for program code storage.
Implementation Method 1
NAND memory uses the Fowler-Nordheim tunneling current. Programming data to the NAND memory requires high voltage, such as at least 15 volts or typically 18 volts, to store charge in the floating gate.
Data Source
AI summary
A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.