Switch Fabric Chip Dual Path Signal Routing

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Solution Overview

Problem

Existing switch devices face high bit error rates and increased costs and power consumption due to long physical traces between switch fabric interface cards (FIC) and remote switch elements (SEs), necessitating additional clock data recovery (CDR) chips as relays.

Innovation Solution

A switch fabric chip with dual transmission paths, allowing it to function as both a relay and a data switch, reducing processing delay and eliminating the need for additional CDR chips by implementing frequency modulation and forward error correction, while using a selector matrix to simplify signal routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FIC is directly connected to remote SE through long physical traces, then connectivity is achieved, but transmission loss increases and bit error rate becomes high

Engineering Contradiction:
Improvedata transmission accuracyVSAvoidphysical trace length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent introduces an intermediate SE (switch element) that acts as a relay between FIC and remote SE. This intermediate SE receives data from FIC, performs clock data recovery and retiming, then forwards to remote SE, effectively breaking the long direct connection into shorter segments and eliminating transmission loss issues

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the clock data recovery function from the traditional CDR chip and integrates it directly into the SE structure. This allows the SE to perform both switching and clock recovery functions, eliminating the need for separate CDR chips and reducing overall system complexity

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If additional CDR chip is configured as relay, then data transmission accuracy improves, but costs and power consumption increase

Engineering Contradiction:
Improvedata transmission accuracyVSAvoidnumber of additional chips
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock data recovery function with the SE function into a single integrated component. The SE now performs both packet switching and clock recovery operations, eliminating the need for separate CDR chips and reducing device complexity while maintaining transmission accuracy

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The SE is designed to perform multiple functions: packet switching, clock data recovery, retiming, and signal regeneration. This multi-functional design replaces what previously required separate dedicated CDR chips, reducing overall system complexity and power consumption

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4084403B1Switch element and switch apparatus
Publication Date: 2024.03.06 HUAWEI TECH CO LTD
  • EP4084403B1 patent drawingFigure 1
  • EP4084403B1 patent drawingFigure 2
  • EP4084403B1 patent drawingFigure 3~4

AI summary

A switch fabric chip and a switch device are provided to improve accuracy of data transmission between a FIC and a remote SE, and reduce costs and power consumption of the switch device. The switch fabric chip includes: a first MAC layer circuit, configured to: perform parsing processing on an input first data stream to obtain a second data stream, and output the second data stream to a processor and a first data selector; the processor, configured to: perform scheduling and switch processing on the second data stream to obtain a third data stream, and output the third data stream to the first data selector; the first data selector, coupled to the first MAC layer circuit and the processor, and configured to: when the first data stream is a data stream that is switched to another switch fabric chip, select to output the second data stream, and when the first data stream is a data stream that is switched to another switch device, select to output the third data stream; and a second MAC layer circuit, coupled to the first data selector, and configured to: perform sending processing on a fourth data stream output by the first data selector.