Multi-stage Switch Fabric for Data Center Connectivity
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Solution Overview
Problem
Existing data center systems are complex and costly, with high latency due to multiple layers of switches performing Ethernet and IP packet processing, leading to poor scalability and increased costs with the addition of more servers.
Innovation Solution
A multi-stage switch fabric with a distributed architecture that provides non-blocking connectivity at line rate across multiple chassis, reducing latency and cost by eliminating redundant packet processing and queuing, and enabling flexible oversubscription and virtualization of resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple layers of switches are used for Ethernet and IP packet processing, then connectivity and routing capabilities are improved, but latency and system complexity increase
Solution Approach 1:
The patent extracts the packet processing function from multiple intermediate switch layers and consolidates it into a single centralized controller. This eliminates redundant Ethernet and IP packet processing at each switch layer, thereby reducing latency while maintaining routing capabilities through the centralized controller's intelligent forwarding decisions.
Solution Approach 2:
The patent merges the functions of multiple switch layers into a single centralized controller that handles all packet processing, routing, and forwarding operations. This consolidation eliminates the need for multiple layers of packet processing, reducing overall system latency while preserving connectivity and routing capabilities through centralized intelligence.
2Adaptability or versatility
If multiple layers of switches are added for routing and connectivity, then network coverage is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts routing and forwarding intelligence from multiple distributed switch layers and concentrates it in a single centralized controller. This eliminates the need for multiple layers of routing-competent devices, reducing system complexity while maintaining extensive network coverage through the controller's comprehensive routing tables and forwarding decisions.
Solution Approach 2:
The centralized controller performs multiple functions that were previously distributed across multiple switch layers, including packet processing, routing decisions, and forwarding. This multi-functional approach reduces the number of devices needed while maintaining network coverage and routing capabilities.
3Productivity
If more servers are added to a data center, then computing capacity is improved, but system cost increases due to additional ports and devices required
Solution Approach 1:
The patent merges the networking functions for multiple servers into a single centralized controller that manages all server connections through a unified switching fabric. This eliminates the need for additional dedicated ports and devices at each server level, allowing computing capacity to scale without proportionally increasing device complexity or cost.
Solution Approach 2:
The centralized controller provides universal connectivity to multiple servers through a single multi-functional device, eliminating the need for separate networking infrastructure at each server. This allows the system to accommodate more servers without requiring additional ports or devices, as the single controller handles all forwarding and routing functions.
Data Source
AI summary
In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.