Switch Fabric Memory Control for Multiprocessor Reliability

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Solution Overview

Problem

In multiprocessor devices, a failure at one processor device renders its associated memory modules inaccessible, limiting resource sharing and allocation between processors.

Innovation Solution

A switch module with a switch fabric and control module allows each processor device to access any memory module, enabling rerouting of memory access requests and maintaining accessibility even if a processor fails, through reconfiguration of link connections based on event indicators from a control module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If each processor device is configured to access only its associated memory modules, then the system structure is simple and easy to manage, but the reliability deteriorates because a processor failure renders its memory modules inaccessible

Engineering Contradiction:
Improvememory accessibilityVSAvoidmemory access configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory control device is designed to perform multiple functions: it can control memory modules associated with a specific processor device and also control memory modules associated with other processor devices. This multi-functionality allows the system to maintain memory accessibility even when a processor fails, as the memory control device can redirect access to healthy processors, thereby improving reliability without significantly increasing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory control device acts as an intermediary between processor devices and memory modules. Instead of direct one-to-one connections, the memory control device mediates access requests, enabling flexible routing of memory access between different processor-memory pairs. This intermediary role allows the system to maintain access to memory modules even when original associated processors fail

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If memory modules are exclusively assigned to specific processor devices, then resource allocation is simple and clear, but the adaptability deteriorates because memory resources cannot be shared or reallocated between processors

Engineering Contradiction:
Improvememory resource sharingVSAvoidresource management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system implements dynamic memory resource allocation where the memory control device can change the association between processor devices and memory modules based on system conditions. Processors can be dynamically added or removed from the system, and the memory control device adjusts the configuration accordingly, allowing memory resources to be reallocated to remaining healthy processors without physical reconfiguration

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory control device is designed to handle multiple processor devices and their associated memory modules universally. It can manage memory access requests from any processor device to any memory module, enabling flexible resource sharing and allocation while maintaining a unified control mechanism that manages complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8055939B2Memory control device and methods thereof
Publication Date: 2011.11.08 ADVANCED MICRO DEVICES INC
  • US8055939B2 patent drawing
  • US8055939B2 patent drawing
  • US8055939B2 patent drawing

AI summary

A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time.