Switch Fabric Memory for High-Throughput Packet Scheduling
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Solution Overview
Problem
Output queued (OQ) packet switch architectures are expensive to build for large N or high-speed data lines due to high memory requirements at each output port, limiting their throughput to less than 60 Gbit/s, while less expensive designs like combined input, fabric, and output queued (CIFOQ) switches often fall short in performance.
Innovation Solution
A packet switching design with memory in the switch fabric and at input ports, utilizing input and output queues, a controller for prioritizing cells, and flow-control mechanisms to emulate OQ switch performance with reduced memory capacity, including a CIFOQ switch architecture with shared or partitioned fabric memory and scheduling mechanisms that ensure highest priority cell transfer and flow-control updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output queued (OQ) packet switch architecture is used, then quality of service (QoS) performance is improved, but device cost and memory requirements increase significantly
Solution Approach 1:
The patent segments the monolithic OQ switch architecture into distributed components: input ports with virtual output queues (VOQs), a shared fabric memory, and output ports. This segmentation allows the system to achieve OQ performance through coordinated distributed operations rather than requiring expensive dedicated memory at each output port.
Solution Approach 2:
The shared fabric memory serves multiple functions: it acts as buffer storage for packets, provides flow control mechanisms, and enables scheduling operations. This multi-functionality reduces the need for separate dedicated components, thereby lowering device cost while maintaining QoS performance.
2Reliability
If output queued (OQ) packet switch architecture is used, then quality of service (QoS) performance is improved, but memory capacity requirements increase
Solution Approach 1:
The patent merges the buffering function with the fabric memory, creating a combined input-fabric-output queued (CIFOQ) architecture. This consolidation eliminates the need for separate buffer memories at each output port, reducing total memory capacity requirements while maintaining QoS guarantees through coordinated scheduling and flow control.
3Ease of manufacture
If combined input, fabric, and output queued (CIFOQ) switch is used, then device cost is reduced, but performance falls short of OQ switch
Solution Approach 1:
The patent implements feedback mechanisms through flow control signals and scheduling algorithms that monitor buffer states and adjust packet transmission accordingly. This feedback enables the CIFOQ architecture to dynamically optimize performance, closing the gap with OQ switches while maintaining lower device cost.
Solution Approach 2:
The patent introduces dynamic scheduling algorithms and adaptive flow control mechanisms that adjust to varying traffic conditions in real-time. This dynamic behavior allows the CIFOQ switch to achieve OQ-level performance by optimally utilizing available resources under different load conditions.
Data Source
AI summary
Packets having at least one cell are switched using input queues, output queues, a switch fabric, and a controller. Each input queue stores cells to be switched, and each output queue stores switched cells. The switch fabric couples the input queues to the output queues and has memory. The switch fabric stores cells moved from the input queues to the switch fabric and stores cells based on the output queues. The controller couples to the input queues and the switch fabric and determines input priorities for cells moving from the input queues to the switch fabric and output priorities for cells moving from the switch fabric to the output queues.