Multi-Stage Switch Fabric with Shared Memory for Data Center Latency

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Solution Overview

Problem

Existing data center systems are complex and costly, with increased latency due to repeated packet processing and queuing at multiple layers of switches, and poor scalability, leading to high costs and inefficiencies as server numbers increase.

Innovation Solution

A multi-stage switch fabric with shared memory devices that acts as a single logical entity, reducing packet processing and queuing overhead by performing classification and scheduling at edge devices, and using a request-grant scheme for congestion management, thereby minimizing latency and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple layers of switches are used for packet processing, then network connectivity and routing capabilities are improved, but latency increases due to repeated packet processing and queuing overhead

Engineering Contradiction:
Improvenetwork connectivityVSAvoidlatency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent extracts packet processing functions from intermediate switch layers and concentrates them at edge devices. By removing unnecessary processing steps from the network core, the system achieves lower latency while maintaining connectivity through the simplified single-hop architecture.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system segments network functions by placing intelligent processing at edge devices rather than distributing it across multiple switch layers. This segmentation allows the network core to focus solely on simple packet forwarding, reducing processing overhead and latency.

Inventive Principle:
Principle #1Segmentation

2Productivity

If more servers are added to increase data center capacity, then service capability is improved, but cost increases due to requiring additional ports and devices at each layer

Engineering Contradiction:
Improvedata center capacityVSAvoidnumber of devices
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple switch layers into a single logical entity, consolidating network infrastructure. This consolidation reduces the total number of devices required while maintaining the ability to support increased server capacity through the edge device classification and scheduling mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single logical switch entity performs multiple functions including packet classification, scheduling, and routing that previously required separate devices at different layers. This multi-functionality reduces device count while supporting scalable server additions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If packet processing is performed at each switch layer, then network control and routing are improved, but processing overhead and cost increase

Engineering Contradiction:
Improvenetwork controlVSAvoidprocessing efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent extracts intelligent packet processing from the network core switches and relocates it to edge devices. This extraction eliminates redundant processing at intermediate layers while maintaining network control capabilities through edge-based classification and scheduling.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of processing packets at every hop through multiple switch layers, the system inverts the approach by making intelligent decisions at the edge and using a simple single-hop core. This inversion dramatically reduces processing overhead while maintaining operational control.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS8340088B2Methods and apparatus related to a low cost data center architecture
Publication Date: 2012.12.25 JUNIPER NETWORKS INC
  • US8340088B2 patent drawing
  • US8340088B2 patent drawing
  • US8340088B2 patent drawing

AI summary

In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.