Switch-FIFO Time Interleaver Layout for Lower Deinterleaver Memory

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Solution Overview

Problem

The DVB-NGH specification lacks a detailed method for generating time-interleaved transmission sequences, and existing time interleavers and deinterleavers are resource-intensive, particularly in terms of memory usage, which is a challenge for implementing efficient communication systems.

Innovation Solution

A time interleaver and deinterleaver system that combines block interleaving and convolutional interleaving, utilizing switches and FIFO memories to efficiently rearrange and de-rearrange cells across interleaving units, with a focus on reducing memory usage and implementing hybrid interleaving and deinterleaving methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional time interleavers and deinterleavers are used, then time interleaving function is achieved, but memory usage increases

Engineering Contradiction:
Improvememory usageVSAvoidtime interleaving function
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The time interleaver is divided into multiple branches, each handling a portion of the input cells. The deinterleaver is segmented into multiple deinterleavers corresponding to each branch. This segmentation allows the system to process cells in parallel across branches, reducing the memory burden on any single component while maintaining the overall time interleaving function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic switching mechanisms where the connection destination of inputs is switched to one end of branches and outputs is switched to another end. This dynamic switching allows the system to adaptively manage data flow and memory requirements, enabling reduced memory usage while preserving the time interleaving functionality through flexible resource allocation.

Inventive Principle:
Principle #15Dynamics

2Reliability

If hybrid interleaving with block and convolutional interleaving is used, then interleaving performance is improved, but device complexity increases

Engineering Contradiction:
Improveinterleaving performanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines block interleaving and convolutional interleaving into a hybrid interleaving system. Multiple branches are merged into a unified structure where each branch can be configured with appropriate interleaving depth. This merging approach maintains the performance benefits of both interleaving types while managing complexity through systematic integration rather than separate independent systems.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hybrid interleaver structure is designed to be universal, capable of supporting different interleaving depths and configurations across its branches. This multi-functionality allows the same basic structure to adapt to various performance requirements without requiring completely different architectures, thereby managing complexity while maintaining versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10938735B2Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
Publication Date: 2021.03.02 PANASONIC HOLDINGS CORP
  • US10938735B2 patent drawing
  • US10938735B2 patent drawing
  • US10938735B2 patent drawing

AI summary

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.