Semiconductor Switch Gate Control for EMI and Switching Loss

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Solution Overview

Problem

Existing electronic circuits for semiconductor switching elements fail to effectively suppress both conductive noise and radiation noise (EMI) while minimizing switching loss.

Innovation Solution

An electronic circuit configuration that includes a current supply circuit, a detection circuit, and a control circuit, utilizing n-type and p-type transistors to dynamically adjust the state of the semiconductor switching element based on detected voltage differential values, aiming to maintain a target differential value that balances noise suppression and loss reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the semiconductor switching element switches state rapidly to reduce switching loss, then switching loss is reduced, but conductive noise and radiation noise increase

Engineering Contradiction:
Improveswitching lossVSAvoidconductive noise and radiation noise
Core Design Contradiction:
Loss of energyVSObject-generated harmful factors

Solution Approach 1:

The patent applies dynamics by making the gate resistance variable rather than fixed. The gate resistance is dynamically adjusted based on the switching state and operating conditions, allowing the system to optimize between switching speed and noise generation. During different phases of switching, the resistance changes to control the rate of voltage change (dV/dt), thereby reducing both switching loss and electromagnetic interference adaptively

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of gate resistance from a constant value to a variable parameter that can be adjusted during operation. By modifying the gate resistance value, the system controls the charging and discharging rate of the gate capacitance, which directly affects the switching speed and the resulting noise. This parameter change enables simultaneous optimization of switching efficiency and noise suppression

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If the gate resistance is increased to suppress noise, then conductive noise and radiation noise are reduced, but switching loss increases

Engineering Contradiction:
Improveconductive noise and radiation noiseVSAvoidswitching loss
Core Design Contradiction:
Object-generated harmful factorsVSLoss of energy

Solution Approach 1:

The patent makes the gate resistance dynamic rather than static. Instead of using a high fixed resistance that would always suppress noise but increase switching loss, the system dynamically adjusts the resistance value based on real-time switching conditions. During voltage transitions, the resistance is optimized to minimize dV/dt and noise, while during steady states, it allows for efficient switching

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action through the oscillating nature of the gate resistance control. The resistance is periodically adjusted in sync with the switching frequency, creating optimal conditions for noise suppression during each switching cycle while maintaining overall switching efficiency. This periodic modulation of resistance allows the system to adapt to different operating phases

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10892749B2Electronic circuit, method, and non-transitory recording medium
Publication Date: 2021.01.12 KK TOSHIBA
  • US10892749B2 patent drawing
  • US10892749B2 patent drawing
  • US10892749B2 patent drawing

AI summary

An electronic circuit of the embodiments includes at least one first n-type transistor, at least one first p-type transistor, a supply circuit, a detection circuit, and a control circuit. The supply supplies current to a control terminal of a semiconductor switching element. The detection circuit acquires a value associated with a voltage at a first terminal of the semiconductor switching element. The control circuit causes one type of transistors of the first n-type transistors and the first p-type transistors to be in the non-driven state and causing at least one of the other type of transistors to be in the driven state, at least based on the value associated with the voltage. The first n-type transistor is electrically connected to a reference potential and the control terminal, and the first p-type transistor is electrically connected to a power supply potential and the control terminal.