Switch Architecture with Ingress Buffering for Low Latency

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Solution Overview

Problem

Modern communication networks face challenges in scalability, low latency, and low frame loss, especially with increasing bandwidth demands from video applications and mobile devices, which can lead to performance degradation and revenue loss due to even small amounts of frame loss.

Innovation Solution

A switch architecture with a packet-based fabric, non-blocking multistage circuit switching network, layered management, ingress buffering with Virtual Output Queues, and lossless fabric control with Head Of Line avoidance, implementing both fast link level and end-to-end flow control to manage traffic and prevent frame loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bandwidth capacity is increased to meet growing data demands, then network throughput is improved, but latency and frame loss increase due to traffic congestion

Engineering Contradiction:
Improvenetwork throughputVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The network fabric is segmented into multiple independent buffering domains (ingress buffers at switch inputs, egress buffers at switch outputs). This segmentation allows different traffic flows to be buffered independently, preventing congestion in one flow from affecting others, thereby maintaining low latency while supporting high throughput through parallel buffer operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Buffers are pre-positioned at both ingress and egress points before traffic congestion occurs. This preliminary buffering capacity allows the system to absorb traffic bursts and regulate flow proactively, preventing latency buildup and frame loss before they occur, rather than reacting after congestion has developed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If buffering capacity is increased to reduce frame loss, then frame loss is reduced, but latency increases due to longer queue wait times

Engineering Contradiction:
Improveframe lossVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The buffering system is divided into multiple independent buffer domains (ingress buffers and egress buffers) that operate semi-independently. This segmentation allows frames to be buffered at the earliest possible point (ingress) without forcing them to wait in long egress queues, thereby reducing both frame loss and latency simultaneously through distributed buffer management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ingress buffer acts as an intermediary between incoming traffic and the switching fabric, absorbing traffic bursts before they propagate through the system. This intermediary buffering prevents downstream congestion and reduces the need for frames to wait in egress buffers, thereby reducing both frame loss and overall latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If network scale is increased to support more devices, then network capacity is improved, but complexity and control difficulty increase

Engineering Contradiction:
Improvenetwork scalabilityVSAvoidcontrol complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The switch is segmented into multiple independent buffering domains (one per input port and one per output port), each with its own buffer management logic. This segmentation allows the system to scale to more ports and higher capacities while maintaining manageable control complexity, as each buffer domain can be controlled independently rather than requiring centralized management of the entire network state.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Buffer management decisions are made preliminarily at ingress points based on local traffic conditions, rather than requiring complex centralized control to manage buffer states throughout the entire network. This preliminary local decision-making enables network scaling while keeping control complexity manageable through distributed autonomy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10728156B2Scalable, low latency, deep buffered switch architecture
Publication Date: 2020.07.28 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US10728156B2 patent drawing
  • US10728156B2 patent drawing
  • US10728156B2 patent drawing

AI summary

A switch architecture includes an ingress module, ingress fabric interface module, and a switch fabric. The switch fabric communicates with egress fabric interface modules and egress modules. The architecture implements multiple layers of congestion management. The congestion management may include fast acting link level flow control and more slowly acting end-to-end flow control. The switch architecture simultaneously provides high scalability, with low latency and low frame loss.