Cascade Switch Latency Compensation for Storage Frame Synchronization

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Solution Overview

Problem

Storage systems, such as RAID systems, experience performance imbalances due to varying frame arrival times caused by differences in storage positions, leading to uneven processing times and potential command sinking issues, which are difficult to manage manually or through complex programming, especially in multi-cascaded setups.

Innovation Solution

A storage apparatus with cascade-connected switches and storages, where at least one switch includes memory for storing latency values corresponding to destination addresses, allowing frames to be transmitted after a delayed time based on these values, ensuring equal latency across the system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If frames are transmitted directly without delay adjustment, then transmission speed is fast, but performance imbalance occurs due to different arrival times at storages

Engineering Contradiction:
Improveframe transmission speedVSAvoidperformance balance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The switch performs preliminary action by calculating and storing latency values for each destination storage before frame transmission occurs. When a frame is received, the switch reads the pre-calculated latency value from the table and applies the appropriate delay, ensuring that frames arrive at all storages simultaneously despite different physical distances. This preliminary preparation of latency data enables the system to maintain both high transmission speed and performance balance.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If manual setting or complex programming is used to control storage performance, then performance balance can be achieved, but time and labor expenses increase

Engineering Contradiction:
Improveperformance balanceVSAvoidtime and labor for management
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The switch performs self-service by automatically calculating latency values based on its position in the cascade connection and storing these values in an internal table. The switch independently determines the appropriate delay for each destination storage without requiring manual configuration or complex external programming. This self-service capability eliminates time and labor expenses while maintaining performance balance across the storage system.

Inventive Principle:
Principle #25Self-service

3Quantity of substance

If many storages are multi-cascaded to increase capacity, then storage capacity increases, but latency variations increase causing larger performance imbalance

Engineering Contradiction:
Improvestorage capacityVSAvoidperformance balance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The switch applies local quality by creating destination-specific latency values tailored to each individual storage's position in the cascade connection. Rather than using a uniform delay for all storages, the switch stores and applies different latency values in its table based on the specific path and distance to each destination storage. This localized approach allows the system to accommodate many multi-cascaded storages while maintaining performance balance by compensating for each storage's unique distance from the computer.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9054948B2Storage apparatus, switch and storage apparatus control method
Publication Date: 2015.06.09 FUJITSU LTD
  • US9054948B2 patent drawing
  • US9054948B2 patent drawing
  • US9054948B2 patent drawing

AI summary

A storage apparatus connectable to a computer for transmitting a frame includes a plurality of switches connected by a cascade connection, and a plurality of storages connected to the plurality of switches, wherein at least one of the plurality of switches includes a memory for storing latency value corresponding to a destination address of the frame, the destination address indicating one of the plurality of storages and the computer of a destination of the frame, the latency value indicating an amount of delaying to begin a transmission of the frame, and a port for executing a process including receiving the frame, reading out the latency value corresponding to the destination address included in the received frame from the memory, and transmitting the frame after a time corresponding to the latency value elapsed.