Switch Leakage Compensation Circuit for ADC Clock Skew
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Solution Overview
Problem
Integrated circuit applications face challenges in maintaining accurate clock timing due to non-ideal transistor behavior, particularly in ADC circuits where switch leakage currents cause voltage droop and time skew, especially at low speeds and across varying process, voltage, and temperature conditions.
Innovation Solution
A delay circuit is introduced with a compensating transistor connected in parallel to a control transistor, bypassing leakage current to maintain capacitor voltage constant, using MOS capacitors and transistors with similar dimensions to match leakage currents, reducing area and fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If transistors are used as switches in ADC circuits, then digital signal processing is enabled, but switch leakage currents cause voltage droop and timing errors
Solution Approach 1:
A compensation transistor is introduced as an intermediary element to counteract the leakage current effect. The compensation transistor is configured to source or sink current that compensates for the switch leakage, thereby maintaining accurate capacitor voltage and clock timing without requiring changes to the primary switching transistors
Solution Approach 2:
The circuit employs feedback mechanisms where the compensation transistor's operation is controlled by signals that respond to the switching state and timing requirements. This feedback ensures that the compensation current dynamically adjusts to maintain voltage stability across varying operating conditions
2Speed
If transistor switches are used to control capacitor charging/discharging, then timing control is achieved, but leakage current causes voltage droop especially at low speeds
Solution Approach 1:
The invention converts the harmful leakage current effect into a beneficial compensation mechanism. By intentionally introducing a compensation transistor that generates an equal and opposite current, the originally harmful leakage effect is transformed into a useful compensation action that maintains voltage stability
Solution Approach 2:
The circuit modifies operating parameters by adjusting the compensation transistor's current based on switching state and timing requirements. This dynamic parameter adjustment ensures optimal compensation across different operating speeds and conditions, preventing voltage droop without sacrificing timing precision
3Reliability
If larger transistors are used to reduce leakage impact, then voltage stability improves, but circuit area increases
Solution Approach 1:
The current compensation function is segmented into a separate compensation transistor rather than requiring larger switching transistors. This segmentation allows the primary switches to maintain their original size for timing precision while the dedicated compensation element handles the leakage counteraction, optimizing the area-efficiency tradeoff
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates capacitor voltage droop, ensuring accurate clock timing and reducing time skew in ADCs, enabling operation across large frequency ranges and various environmental conditions.
Implementation Method 1
a compensating transistor configured to passively bypass a leakage current around a capacitor that connects in series with a control transistor
Implementation Method 2
a capacitor (C 0 ') connected between a reference node and a second node (b 0 ')
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
Apparatus and associated methods relating to a switch leakage compensation delay circuit (405a) include a compensating transistor (To) configured to passively bypass a leakage current around a capacitor (Co) that connects in series with a control transistor (Mo). In an illustrative example, the capacitor (Co) and the compensating transistor (To) may be connected in parallel between a first node (ao) and a second node (bo). The compensating transistor (To) gate may be tied, for example, directly to its source and to the second node (bo). The control transistor (Mo) may connect its drain to the second node (bo). When a control signal turns off the control transistor (Mo), a leakage current of the control transistor (Mo) may be supplied from a leakage current of the compensating transistor (To) such that the voltage across the capacitor (Co) may be maintained substantially constant. The delay circuit (405a) may advantageously mitigate the capacitor's (Co) voltage droop to reduce clock time skew, for example, in low speed interleaved ADC operation.