Switch Module Memory Structure and Per-Destination Queue Flow Control
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Solution Overview
Problem
Current large-capacity IP routers face challenges in scalability and cost-effectiveness due to memory and interconnection bottlenecks, particularly in multi-stage switch architectures, where memory size limitations and flow control mechanisms are inefficient, leading to potential cell overflow and increased complexity.
Innovation Solution
The solution involves sharing cell memory across input and output links, setting a queue threshold to accommodate round-trip delay, and implementing a per-link credit-based flow control scheme that sends credit information via cell headers, simplifying implementation and reducing interference between links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cell memory is dedicated to each input-output link, then memory availability for each link is guaranteed, but memory utilization efficiency deteriorates and overall memory size requirements increase
Solution Approach 1:
The patent merges previously dedicated per-link memory resources into shared memory pools at input and output sides. Multiple links share common memory resources through credit-based flow control mechanisms, allowing dynamic allocation and improving overall memory utilization while maintaining sufficient availability for each link through credit tracking.
Solution Approach 2:
The patent makes memory resources universal by allowing the same memory pool to serve multiple input links and multiple output links. The shared memory structure enables each memory resource to be accessed by multiple links dynamically, transforming dedicated single-function memory into multi-functional shared memory that serves the entire switch fabric.
2Reliability
If per-link flow control is implemented, then cell overflow is prevented, but implementation complexity and interference between links increases
Solution Approach 1:
The patent segments flow control into independent credit-based mechanisms for each link while sharing common memory resources. Each link has its own credit counter and flow control logic, but these segmented controls operate on shared memory pools rather than dedicated memory, reducing overall complexity while maintaining overflow prevention for each individual link.
Solution Approach 2:
The patent implements self-service flow control where each link autonomously manages its own credit counters and makes independent send/receive decisions based on its own credit status. This decentralized self-service approach eliminates the need for centralized arbitration and reduces interference between links, simplifying the overall flow control mechanism while maintaining reliable overflow prevention.
3Productivity
If memory size is increased to handle large capacity switches, then routing capacity increases, but cost and complexity of memory and interconnection increases
Solution Approach 1:
The patent transitions from a flat dedicated-memory-per-link structure to a hierarchical shared-memory structure with input memory pools and output memory pools. This dimensional reorganization allows memory resources to be shared across multiple links in a structured manner, enabling large routing capacity without linearly increasing memory size or interconnection complexity.
Data Source
AI summary
To use the memory space more effectively, cell memory can be shared by an input link and all output links. To prevent one flow from occupying the entire memory space, a threshold may be provided for the queue. The queue threshold may accommodate the RTT delay of the link. Queue length information about a downstream switch module may be sent to an upstream switch module via cell headers in every credit update period per link. Cell and/or credit loss may be recovered from. Increasing the credit update period reduces the cell header bandwidth but doesn't degrade performance significantly. Sending a credit per link simplifies implementation and eliminates interference between other links.