Switch Network Derivation for Multiple-Valued Logic
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Solution Overview
Problem
Existing methods for designing integrated circuits with multiple-valued functions result in networks with excessive serial switches, leading to increased area, power consumption, and delay, as they fail to optimize the number of serial transistors in switch networks.
Innovation Solution
A method is developed to derive switch networks for multiple-valued functions by selecting networks with the lowest number of serial switches, using covering tables and prime implicant cubes to minimize serial switches while maintaining functionality, and optimizing network structure by sharing switches and rearranging paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional methods are used to derive switch networks for multiple-valued functions, then the networks can be obtained, but the number of serial switches increases leading to increased area, power consumption, and delay
Solution Approach 1:
The patent applies multi-functionality by using a single switch network to implement multiple-valued logic functions (more than two output values) simultaneously, rather than requiring separate networks for each function value. This universal approach reduces the total number of serial switches needed compared to conventional methods that would require multiple binary logic networks
Solution Approach 2:
The patent changes the parameter space by extending from binary (2-valued) logic to multiple-valued logic (m-valued where m>2). This parameter change allows the network to represent more states simultaneously, reducing the depth of serial switch stacks required and thereby decreasing delay while maintaining functionality
2Device complexity
If conventional methods are used to derive switch networks, then the networks can be obtained, but the area occupied by the network increases due to excessive serial switches
Solution Approach 1:
By designing a switch network that handles multiple-valued functions in a unified manner, the patent reduces the total switch count and consequently the area required. Instead of implementing separate binary logic networks for each function value, a single multi-valued network achieves the same computational capability with reduced area overhead
Solution Approach 2:
The patent merges multiple function implementations into a single switch network structure. By combining the logic paths for different output values into one integrated network, the patent eliminates redundant switches and reduces the overall area occupied by the circuit implementation
3Device complexity
If conventional methods are used to derive switch networks, then the networks can be obtained, but power consumption increases due to excessive serial switches
Solution Approach 1:
The multi-valued switch network reduces power consumption by minimizing the number of serial switches required to implement the logic function. Fewer serial switches mean less capacitive loading and fewer switching events, directly reducing dynamic power consumption while maintaining the same computational functionality
Data Source
AI summary
A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as standard cells implementations of combinational logic cells. The minimum number of switches can also be used as a criterion for technology mapping devoted to automatic cell generation. The method is based on the use of a covering table to derive a sum of products where individual cubes have a minimum literal count.