Switch Memory Overflow Prevention for RoCE Deadlock Control
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Solution Overview
Problem
Deadlocks in network topologies due to cyclic buffer dependencies caused by Priority-based Flow Control (PFC) in RDMA over Converged Ethernet (RoCE) networks, leading to zero throughput and non-recoverable standstill situations.
Innovation Solution
Implementing a Deadlock Prevention Module (DPM) that generates a finite state machine to analyze routing decisions, identifies memory overflow states, and transmits anti-deadlock rules to switches to prevent forbidden routing, thereby reducing and preventing deadlocks by enforcing forbidden routing rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Priority-based Flow Control (PFC) is used in RoCE networks to ensure lossless delivery, then packet loss is avoided, but cyclic buffer dependencies occur leading to deadlocks
Solution Approach 1:
The system performs preliminary analysis of routing decisions using a finite state machine to identify potential deadlock paths before they occur. Anti-deadlock rules are generated in advance and transmitted to switches, enabling them to prevent cyclic buffer dependencies before they form, thus maintaining throughput while preserving lossless delivery guarantees.
Solution Approach 2:
The system continuously monitors switch states and buffer allocations, using feedback from the finite state machine analysis to dynamically generate and update anti-deadlock rules. This feedback mechanism allows the network to adapt to changing conditions while preventing deadlocks, ensuring both reliability and productivity are maintained.
2Adaptability or versatility
If traditional routing rules are used without deadlock prevention, then routing flexibility is maintained, but memory overflow states occur leading to deadlocks
Solution Approach 1:
The finite state machine acts as an intermediary between traditional routing rules and deadlock prevention. It analyzes routing decisions without restricting flexibility, identifying potential deadlock paths while allowing valid routing options. The anti-deadlock rules generated serve as a mediator layer that guides switches away from problematic states while maintaining overall routing adaptability.
Solution Approach 2:
The system changes the parameter of routing rule enforcement by introducing conditional restrictions based on finite state machine analysis. Instead of applying fixed rigid rules or completely flexible routing, the system dynamically adjusts routing behavior by generating anti-deadlock rules that modify parameter constraints only when necessary to prevent deadlocks, thus preserving flexibility while ensuring reliability.
3Measurement precision
If finite state machine analysis is performed to identify deadlock paths, then deadlock prevention accuracy is improved, but computational complexity increases
Solution Approach 1:
The finite state machine analysis is segmented into manageable components: individual switch state analysis, buffer allocation tracking, and routing decision evaluation. This segmentation allows the complex analysis to be performed in discrete steps across multiple switches, reducing the computational burden on any single device while maintaining high detection accuracy through coordinated analysis.
Data Source
AI summary
Example embodiments disclose a method for avoiding deadlock in a network includes generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches, analyzing the finite state machine, determining at least one memory overflow state based on the analyzing, generating at least one anti-deadlock rule in response to determining the at least one memory overflow state, and transmitting the at least one anti-deadlock rule to the plurality of switches.