Network Switch Payload Bypass for Low-Latency Packet Forwarding
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Solution Overview
Problem
Ethernet network switches experience increased latency due to intra-packet delays, which can lead to packet drops and reduced competitiveness in the market, especially with increasing internal processing complexity.
Innovation Solution
A network switch design that includes a first data path to separate and bypass payload cells from header processing, a traffic manager with separate control and data paths to manage timing and storage, and a second data path for jitter compensation, ensuring smooth packet transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If internal processing complexity of switches increases to handle more sophisticated packet management, then packet forwarding capability is improved, but internal delays increase resulting in higher latency
Solution Approach 1:
The packet processing is segmented into two independent paths: a control path that handles header processing and timing coordination, and a data path that handles payload transmission. This segmentation allows the control path to manage complex forwarding decisions while the data path maintains simple, low-latency transmission, resolving the contradiction between processing capability and latency.
Solution Approach 2:
The control path performs preliminary actions by processing packet headers and determining forwarding decisions before the payload data needs to be transmitted. This advance processing allows the data path to immediately transmit packets without waiting for complex processing, reducing overall latency while maintaining sophisticated packet management capabilities.
2Reliability
If the switch waits for sufficient time after SOP arrival to account for intra-packet delays, then packet transmission accuracy is improved, but overall latency increases
Solution Approach 1:
A timing coordination mechanism acts as an intermediary between the control path and data path, precisely managing when payload cells should be transmitted. This intermediary coordinates the timing of control signals with data transmission, ensuring that sufficient time is allocated for intra-packet delays without requiring the entire switch to wait, thus maintaining both accuracy and reducing unnecessary latency.
3Speed
If payload cells bypass ingress processing for the packet header, then processing speed is improved, but timing synchronization becomes more difficult
Solution Approach 1:
The control path generates timing coordination signals that provide feedback to the data path, informing it when bypassed payload cells should be transmitted. This feedback mechanism ensures that even though payload cells skip the header processing path, their transmission is precisely synchronized with the overall packet timing requirements, resolving the synchronization complexity through active coordination.
Data Source
AI summary
A network switch comprises a first data path configured to separate a header from a payload of an incoming packet, the first data path is characterized by a reduced latency for cells of the payload without a first processing delay associated with the header in the second data path. The network switch also includes a controller configured with a first control path to transmit a control bus carrying control signals for individual cells and a second control path to transmit a data bus carrying the header and the payload, wherein the control bus is transmitted before the data bus. The network switch also includes a second data path configured to receive the control bus and the data bus separately, and to store the cells temporarily for managing the timing of the cells and handling a second processing delay associated with the header in the second data path before transmitting the packet.