Switch Scheduler Latency Reduction via Parallel-Wrapped Wave Front Arbiter
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Solution Overview
Problem
Large switches with many input and output ports face challenges in determining a schedule quickly due to increasing computation time and high latency, especially under light loads, as existing schedulers require significant time for maximal matching and are complex to implement.
Innovation Solution
A scheduler that uses a parallel-wrapped wave front arbiter (PWWFA) technique with a fast-scheduling method, such as the leave-one or remove-all scheme, to assign additional requests and reduce latency by allowing requests from previous time intervals, and pipelined calculations to determine schedules during each data cell time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a complicated scheduler is used to determine maximal matching between input ports and output ports, then the matching accuracy is improved, but the computation time and latency increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing match information in content addressable memory (CAM) tables before scheduling decisions are needed. The CAM tables are updated in advance with potential matching pairs of input and output ports, allowing the scheduler to quickly retrieve pre-computed matches rather than performing complex real-time calculations. This reduces computation time while maintaining matching accuracy.
Solution Approach 2:
The scheduling problem is segmented into multiple independent CAM tables, each handling specific matching scenarios. Instead of using a single complex scheduler, the patent divides the matching task across multiple simpler CAM structures that can be queried and updated independently. This segmentation allows parallel processing of matching decisions, reducing overall computation time while achieving maximal matching.
2Productivity
If the number of input ports and output ports increases to handle higher throughput, then the switch capacity is improved, but the computation time for determining schedules increases significantly
Solution Approach 1:
The patent replaces the mechanical computation process with an electronic memory-based system. Instead of using traditional computational algorithms that process scheduling decisions sequentially, the invention uses content addressable memory (CAM) structures that perform parallel pattern matching electronically. This substitution allows the system to handle increased port counts and higher throughput without proportionally increasing computation time, as the CAM tables can be queried and updated in parallel regardless of the number of ports.
3Productivity
If a complicated scheduler is used to ensure maximal matching, then the resource utilization is improved, but the device complexity increases
Solution Approach 1:
The patent uses copying by creating multiple copies of the scheduling logic in the form of identical CAM table structures. Each CAM table contains copies of matching information for different input-output port combinations. Instead of implementing a single complex scheduler with diverse logic, the system uses multiple simple, identical CAM structures that can be uniformly queried and updated. This copying approach maintains high resource utilization through maximal matching while keeping individual scheduler components simple and manageable.
Data Source
AI summary
Embodiments of a scheduler for a switch, where the switch is configured to couple input ports to output ports are described. During operation, the scheduler may determine a schedule based on a group of requests, associated with multiple data streams, that are received for the output ports of the switch, where the schedule matches input ports to output ports of the switch for a given data cell time. Note that the schedule may be determined using an arbitration technique during a time interval. Moreover, the scheduler may assign an additional request, which was received at a time that precedes a current time by less than the time interval, to a portion of the switch which is available in the schedule, thereby reducing a latency of the scheduler.