Switch-Based Time Interleaver Branching for Lower Deinterleaver Memory

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Solution Overview

Problem

The DVB-NGH specification lacks a detailed method for generating time-interleaved transmission sequences, and existing time interleavers and deinterleavers are resource-intensive, particularly in terms of memory usage, which is a challenge for implementing efficient communication systems.

Innovation Solution

A time interleaver and deinterleaver system that combines block and convolutional interleaving, utilizing switches and FIFO memories to efficiently rearrange and deinterleave cells across multiple branches, reducing memory usage and enabling hybrid interleaving and deinterleaving, with specific addressing schemes for row-column block interleavers and block interleavers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional time interleavers and deinterleavers are used, then time interleaving functionality is achieved, but memory usage becomes excessive and resource-intensive

Engineering Contradiction:
Improvememory usageVSAvoidinterleaving functionality
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The time interleaver is divided into multiple parallel branches (first branch, second branch, third branch, fourth branch) that process different portions of the input signal simultaneously. Each branch contains its own delay element and switch, allowing the system to achieve the required interleaving depth through parallel processing rather than requiring a single large memory structure. This segmentation reduces the peak memory usage while maintaining the overall interleaving functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs dynamic switching mechanisms where switches (540, 550) dynamically change connection destinations based on the processing stage. The switches sequentially connect to different branches at different time intervals, enabling the system to reuse the same physical resources (delay elements, FIFO memories) across multiple time slots. This dynamic allocation of resources reduces the total memory requirement compared to static memory-based approaches.

Inventive Principle:
Principle #15Dynamics

2Reliability

If hybrid interleaving combining block and convolutional interleaving is implemented, then interleaving performance is improved, but device complexity increases

Engineering Contradiction:
Improveinterleaving performanceVSAvoidinterleaver structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines block interleaving and convolutional interleaving into a hybrid structure where block interleaving is achieved through the parallel branch arrangement and convolutional interleaving is achieved through the sequential switching and delay elements within each branch. This merging of two interleaving techniques into a unified structure achieves the performance benefits of both methods while avoiding the need for separate, independent interleavers, thus managing device complexity more effectively.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The delay elements and FIFO memories within each branch serve multiple functions: they provide both the block interleaving effect (through parallel branch processing) and the convolutional interleaving effect (through sequential switching and time-delayed output). This multi-functionality reduces the need for dedicated components for each interleaving type, thereby reducing overall device complexity while maintaining hybrid interleaving performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11611515B2Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
Publication Date: 2023.03.21 PANASONIC HOLDINGS CORP
  • US11611515B2 patent drawing
  • US11611515B2 patent drawing
  • US11611515B2 patent drawing

AI summary

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.