Switch Transistor Channel Etching with Gradually Reducing Plasma Energy
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Solution Overview
Problem
The existing 5 times lithography process for TFT-LCD production results in poor electrical properties of thin film transistors due to excessive etching energy damaging the a-Si layer and exposure to plasma during channel formation, leading to unreliable transistor performance.
Innovation Solution
A method involving sequential plasma etching with gradually reducing energy and concentration to form the channel of the switch transistor, where the etching process is divided into multiple steps with decreasing power and gas flow, minimizing damage to the amorphous silicon layers and improving etching precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one step etching method is used with same gas flow, same power and same pressure to etch a-Si layer and n+ a-Si layer, then the etching process is simpler and more suitable for mass production, but the etching energy is too powerful causing the a-Si layer to be destroyed and poor electrical properties
Solution Approach 1:
The etching process is divided into two distinct steps: first etching the n+ a-Si layer with higher power, then etching the a-Si layer with lower power. This segmentation allows each layer to be etched with appropriate energy levels, preventing damage to the a-Si layer while maintaining production efficiency.
Solution Approach 2:
The patent dynamically adjusts etching parameters (power, gas flow) between different etching steps. The first etching step uses higher power for the n+ a-Si layer, while the second step uses lower power for the a-Si layer. This dynamic parameter adjustment resolves the contradiction between production efficiency and device reliability.
2Ease of manufacture
If over etching is performed with same parameters after channel formation, then the etching process is simpler, but the channel is bombarded by dry etching plasma causing destruction of a-Si layer
Solution Approach 1:
The patent applies different etching conditions to different stages of the etching process. The first etching step targets the n+ a-Si layer with higher power, while the second step targets the a-Si layer with lower power and reduced gas flow. This local quality adjustment prevents plasma bombardment damage to the channel while maintaining manufacturing simplicity.
3Manufacturing precision
If the channel is exposed outermost after formation, then the channel structure is clearly defined, but the channel is bombarded by plasma from CVD process further damaging electrical properties
Solution Approach 1:
The patent performs preliminary protective etching of the a-Si layer before the channel is fully exposed and before subsequent CVD processes. By etching the a-Si layer with controlled, lower power in the second etching step, the channel structure is defined while simultaneously protecting it from future plasma bombardment during CVD deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes damage to the switch transistor and enhances its electrical properties by reducing etching strength gradually, leading to improved reliability and performance.
Implementation Method 1
the etching process is a dry plasma etching
Implementation Method 2
the channel 7 will be bombarded by dry etching plasma
Data Source
AI summary
The present invention discloses a method for preparing switch transistor comprising: sequentially forming a control electrode, an insulation layer, an active layer, and a source/drain metal layer of the switch transistor on a glass substrate; patterning the source/drain metal layer to expose the active layer; and proceeding an etching process to the exposed active layer in a way of gradually reducing etching rate to form a channel of the switch transistor. The present invention further discloses an equipment for etching the switch transistor. In the way mentioned above, the present invention can minimize the damages to the switch transistor and improve the reliability of the switch transistor.