Switchable Bit-Line Pair Via ROM Design
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Solution Overview
Problem
Conventional Via ROMs require dummy poly gates, leading to larger bit-cell sizes and reduced sensing speed, which hinders their ability to meet the demands of high-speed memory applications.
Innovation Solution
A switchable bit-line pair Via ROM design that eliminates dummy poly gates by using differential bit-line pairs and switching transistors with shared doping regions, allowing for faster sensing and reduced bit-cell size to 1 poly-pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If dummy poly gates are used for diffusion isolation in conventional Via ROMs, then diffusion isolation is achieved, but bit-cell size increases to 1.5 poly-pitch
Solution Approach 1:
The invention extracts and removes the dummy poly gates from the conventional Via ROM structure. By eliminating these unnecessary isolation elements and using shared doping regions between adjacent transistors, the bit-cell size is reduced from 1.5 poly-pitch to 1 poly-pitch while maintaining proper diffusion isolation through the shared doping architecture.
2Speed
If dummy poly gates are used for diffusion isolation, then isolation is provided, but sensing speed decreases
Solution Approach 1:
By removing the dummy poly gates that slow down sensing operations, the invention achieves faster sensing speed. The shared doping region architecture provides sufficient isolation without the speed-penalty imposed by dummy poly gates, enabling the memory to meet high-speed ROM requirements.
3Area of stationary object
If conventional Via ROM structure is used with dummy poly gates, then diffusion isolation is achieved, but bit-cell area increases
Solution Approach 1:
The invention merges the doping regions of adjacent transistors into shared doping regions. This consolidation eliminates the need for dummy poly gates while maintaining diffusion isolation, as the shared doping architecture inherently provides the necessary electrical isolation between adjacent memory cells.
Data Source
AI summary
A semiconductor memory includes: a first switching transistor, wherein the first switching transistor has a first terminal, a second terminal, and a third terminal, and the second terminal is coupled to a first word-line; a first differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the first terminal of the first switching transistor for storing first information; and a second differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the third terminal of the first switching transistor for storing second information.