Switchable On-Die ECC Engine Architecture
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Solution Overview
Problem
On-die error correction engines in memory systems can introduce additional errors and delays when faced with a high number of errors beyond their correction capability, leading to suboptimal performance and reliability.
Innovation Solution
Implementing a switchable ECC engine architecture that allows the on-die ECC engine to be disabled and replaced by a system-level ECC engine, which can provide error correction across multiple memory dies, thereby avoiding additional errors and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an on-die ECC engine is used to correct errors in memory cells, then error correction capability is provided, but additional errors may be introduced when the number of errors exceeds the ECC engine's correction capability
Solution Approach 1:
The patent implements a switchable ECC engine architecture that can dynamically transition between on-die ECC engine and system-level ECC engine based on real-time error conditions. This dynamic switching allows the system to adapt to varying error rates and select the most appropriate error correction mechanism, preventing the introduction of additional errors when error counts exceed correction capabilities.
Solution Approach 2:
The patent introduces a switchable architecture as an intermediary mechanism between the on-die ECC engine and the memory system. This intermediary allows seamless transition to a system-level ECC engine when needed, acting as a mediator that prevents harmful effects while maintaining the benefits of on-die error correction under normal conditions.
2Reliability
If an on-die ECC engine operates continuously to correct errors, then error correction is maintained, but system performance and speed are reduced due to processing delays
Solution Approach 1:
The switchable ECC engine architecture enables dynamic adjustment of error correction processing based on actual system needs. When error rates are low or the on-die engine is sufficient, the system operates at full speed without unnecessary processing delays. The dynamic switching mechanism ensures that the heavier processing of a system-level ECC engine is only activated when truly necessary, maintaining optimal performance under normal conditions.
Solution Approach 2:
The system changes operational parameters by switching between different ECC engine configurations based on error conditions. This parameter change allows the system to optimize between error correction thoroughness and processing speed, selecting the appropriate correction level that matches the actual error situation rather than always using the most comprehensive correction method.
3Reliability
If an on-die ECC engine is always enabled to provide error correction, then memory reliability is improved, but the system cannot adapt to conditions where a system-level ECC engine would be more effective
Solution Approach 1:
The patent implements a dynamic switching mechanism that enables the system to adapt between on-die and system-level ECC engines based on real-time conditions. This dynamic adaptability allows the system to optimize memory reliability by selecting the most effective error correction approach for the current error pattern and system state, rather than being locked into a single fixed configuration.
Solution Approach 2:
The switchable ECC engine architecture provides multi-functionality by enabling the system to utilize both on-die and system-level ECC engines as needed. This universal approach allows a single memory system to handle diverse error conditions effectively, combining the advantages of both localized fast correction and comprehensive system-level correction capabilities.
Data Source
AI summary
Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.