Switchable Per-Lane Bit Error Counting Circuit
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Solution Overview
Problem
Existing error detection techniques in integrated circuits require excessive hardware and fail to accurately determine the location and nature of errors, leading to undetected corruption that can cause catastrophic failures.
Innovation Solution
A switchable error detection system that uses a deserializer unit to convert serial data to parallel, a selection circuit to choose data lanes for error checking, and an error checking unit to compare data to an expected pattern, allowing for high-resolution error detection with reduced hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error detection techniques are used to detect all data transmission errors, then error detection coverage is improved, but hardware complexity and resource requirements increase excessively
Solution Approach 1:
The patent divides the data transmission system into multiple separate data lanes, with each lane having its own error detection mechanism. This segmentation allows the system to detect errors in specific lanes without requiring comprehensive error checking circuitry for all lanes simultaneously, thereby reducing overall hardware complexity while maintaining reliable error detection coverage.
2Measurement precision
If comprehensive error checking is performed on all data lanes simultaneously, then error detection precision is improved, but hardware resources and power consumption increase
Solution Approach 1:
The patent implements dynamic error checking where the error detection mechanism can be selectively enabled or disabled for different data lanes based on system requirements. This dynamic approach allows high error detection precision when needed in specific lanes while conserving hardware resources and power when comprehensive checking is not required, resolving the contradiction between precision and resource consumption.
3Measurement precision
If error detection is performed on every data lane, then location specificity of errors is improved, but the amount of error checking circuitry required increases excessively
Solution Approach 1:
The patent employs a universal error detection approach where a single error detection circuit can be applied to multiple data lanes through selective activation. This multi-functional design allows the system to achieve error location specificity for individual lanes when needed, while avoiding the need for dedicated error checking circuitry for every lane, thereby reducing overall device complexity.
Data Source
AI summary
Systems, methods, and apparatuses for error checking are disclosed. In one embodiment, an error checking system is used on a device that has a plurality of parallel data lanes as inputs. It may be desired to provide an error checking system with sufficient resolution to detect single-bit errors, determine how many bits are in error, and/or determine which bit(s) of a parallel data lane are in error. In one embodiment, the present disclosure provides for switchable error checking through the use of a multiplexor configured to select a particular data lane for error checking. This switchable error checking may provide benefits such as low cost, low power consumption, and/or low size.