Switchable FIFO-RAM Storage Module for Radar SoC Data Bursts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In system on chips (SOCs) for radar systems, the high instantaneous throughput rate of chirp-based, bursty data leads to increased bus load and reduced data processing speed due to the need for large FIFO memories and additional memory for caching, which enlarges the SOC area and hinders efficient data processing.
Innovation Solution
A SOC with a storage module that is dynamically switchable between a FIFO mode and a memory mode, allowing direct data processing and reducing the need for additional memory caching, thereby reducing bus load and increasing data processing speed without enlarging the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacity of the FIFO is designed to fully cache single burst transmission data, then the data caching capability is improved, but the area of the SOC increases significantly
Solution Approach 1:
The storage module dynamically switches between FIFO mode and memory mode based on real-time data access requirements. In FIFO mode, it operates as a first-in-first-out buffer for high-speed data streaming; in memory mode, it provides random access capability. This dynamic reconfiguration allows the same hardware resource to serve multiple functions, reducing the need for separate dedicated memory components and thereby reducing overall SOC area while maintaining adequate data caching capability.
Solution Approach 2:
The storage module is designed to perform multiple functions: it can operate as a FIFO buffer for high-speed data capture, as a randomly accessible memory for processing, and can be configured in different depth modes. This multi-functionality eliminates the need for separate dedicated FIFO and memory components, reducing the total area required in the SOC while ensuring both data caching and processing needs are met.
2Reliability
If additional memory of the same size as burst transmission data is allocated, then the data caching capability is improved, but the area of the SOC increases
Solution Approach 1:
The storage module dynamically reconfigures between FIFO mode and memory mode based on operational requirements. When burst data arrives, it operates in FIFO mode to capture data at high speed. When processing is needed, it switches to memory mode to provide random access. This dynamic behavior allows one storage module to replace what would traditionally require separate dedicated FIFO and memory components, reducing total SOC area.
Solution Approach 2:
The invention merges the functionality of separate FIFO buffer and memory components into a single unified storage module. This storage module can be configured to provide either FIFO operation or random access memory operation, combining the capabilities of what would traditionally require two separate components into one, thereby reducing the area occupied in the SOC.
3Adaptability or versatility
If data is transferred from the FIFO to the memory before processing, then the data access flexibility is improved, but the bus load increases and data processing speed decreases
Solution Approach 1:
The storage module can dynamically switch between FIFO mode and memory mode based on the processing stage requirements. During data capture, it operates in FIFO mode to accept high-speed input. When the processor needs to access data, it switches to memory mode, allowing the processor to read data directly from the storage module without requiring a separate transfer step. This eliminates the intermediate data transfer step, reducing bus load and accelerating processing speed.
Solution Approach 2:
The invention extracts the intermediate data transfer step from the traditional data flow. Instead of transferring data from a dedicated FIFO to a dedicated memory before processing, the storage module provides both FIFO buffering and random access capabilities in one component. The processor can directly access data in memory mode without requiring a separate transfer operation, eliminating this intermediate step and its associated bus load and time delay.
4Reliability
If a large capacity FIFO is used to cache burst transmission data, then the data buffering capability is improved, but the bus load increases
Solution Approach 1:
The storage module dynamically switches between FIFO mode for buffering and memory mode for processing. When buffering burst data, it operates in FIFO mode with deep buffering capability. When the processor needs data, it switches to memory mode, allowing direct access without requiring data to be paged through the bus in large batches. This reduces the sustained bus load while maintaining the ability to buffer large amounts of burst data.
Solution Approach 2:
The storage module performs preliminary data buffering in FIFO mode during the burst transmission phase, capturing all incoming data locally without requiring continuous bus access. Then, when processing is needed, it switches to memory mode and provides data to the processor in a controlled manner. This preliminary buffering action separates the high-speed data capture phase from the processing phase, reducing the bus load during the critical buffering period.
Data Source
AI summary
Disclosed is a SOC and a method for data storage thereof. The SOC includes a storage module that is controllably and dynamically switchable between a first storage mode and a second storage mode, and a processing module. In the first storage mode, data in the storage module is accessible by the processing module in a first-in-first-out order; and in the second storage mode, data in the storage module is addressably accessible by the processing module. The embodiment of the present disclosure fully utilizes RAM resources of FIFO to act as a SOC memory, and achieves time-sharing multiplexing of RAM to realize that, for a batch transmission scenario with a large amount of data and a high speed, the storage module is capable of being switched between the first storage mode and the second storage mode.