Switchable I2S Interface Multiplexer FIFO Shift Register

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Solution Overview

Problem

Conventional I2S interfaces are limited in handling multiple microphones, requiring multiple interfaces and causing synchronization issues, leading to inefficiencies in product development and increased costs.

Innovation Solution

A switchable I2S interface incorporating a multiplexer, switchable FIFO memory, and switchable shift register that generates switching signals to dynamically switch between transmission and receiving control circuits, allowing for efficient use of a single interface for multiple audio signals and reducing the need for multiple interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple I2S interfaces are used to handle multiple microphones, then the capability to receive audio signals from multiple microphones is improved, but the device complexity and synchronization difficulty increase

Engineering Contradiction:
Improvecapability to handle multiple microphonesVSAvoidnumber of I2S interfaces required
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The I2S interface is designed with a switchable FIFO memory that can dynamically switch between transmission and receiving modes. This allows a single I2S interface to handle multiple microphones by alternating between receiving audio signals from different microphones at different time slots, eliminating the need for multiple dedicated interfaces and reducing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a dynamic switching mechanism where the FIFO memory can change its operational mode (transmission/receiving) based on control signals. This dynamic capability enables the interface to adaptively handle multiple microphones by switching between different receiving tasks, providing versatility without requiring multiple static interfaces

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If multiple I2S interfaces are used to handle multiple microphones, then the capability to receive audio signals from multiple microphones is improved, but the synchronization difficulty and processing time increase

Engineering Contradiction:
Improvecapability to handle multiple microphonesVSAvoidsynchronization processing time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The dynamic switching capability of the FIFO memory allows the system to sequentially handle multiple microphones through a single interface. By rapidly switching between microphones in a time-division manner, the system achieves multi-microphone capability without the synchronization overhead of coordinating multiple independent interfaces, reducing processing time

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If a conventional unidirectional FIFO memory is used, then the simplicity of unidirectional transmission is maintained, but the transmission efficiency and resource utilization deteriorate when only one direction is needed

Engineering Contradiction:
Improvesimplicity of unidirectional transmissionVSAvoidtransmission efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The FIFO memory is designed with dynamic controllability, allowing it to switch between transmission and receiving modes based on actual needs. When only unidirectional transmission is required, the system activates only the transmission path, maintaining operational simplicity. When bidirectional communication is needed, both paths can be activated, improving overall transmission efficiency and resource utilization

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11314682B2Switchable I2S interface
Publication Date: 2022.04.26 NUVOTON
  • US11314682B2 patent drawing
  • US11314682B2 patent drawing
  • US11314682B2 patent drawing

AI summary

A switchable I2S interface including a multiplexer, a switchable FIFO memory and a switchable shift register, is disclosed. The multiplexer receives a transmission instruction or a receiving instruction, and configured to generate a switching signal according to the received instruction. The switchable FIFO memory is connected to the multiplexer and receives the switching signal, and comprise a transmission control circuit and a receiving control circuit. According to the switching signal, the switchable FIFO memory switches on the transmission control circuit to transmit the audio output signal, or switches on the receiving control circuit to receive the audio input signal. The switchable shift register is connected to the switchable FIFO memory, and receives and temporarily stores the audio output signal and the audio input signal.