Switchable Oscillator Circuit for Low-Power Clock Generation
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Solution Overview
Problem
Existing oscillator circuits face challenges in reducing power dissipation, particularly when operating in low-frequency modes, and require independent provision of built-in oscillators and PLLs, making them inefficient.
Innovation Solution
An oscillator circuit that switches its oscillating frequency between high and low frequencies in response to a frequency selection signal, with a frequency divider circuit generating a sub-clock signal with a predetermined division ratio, allowing for synchronized switching and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a built-in oscillator operates at high frequency to provide a main clock signal, then the clock signal frequency is sufficient for CPU operation, but power dissipation increases and cannot be reduced in low-speed operation modes
Solution Approach 1:
The oscillator circuit dynamically switches between high-frequency and low-frequency operation modes based on system requirements. A frequency selection signal controls switching between a high-frequency oscillation circuit (for CPU operation) and a low-frequency oscillation circuit (for power-saving modes), allowing the system to adapt its operating frequency and reduce power consumption during low-speed operations.
Solution Approach 2:
The oscillator system is divided into separate high-frequency and low-frequency oscillation circuits. The high-frequency circuit generates main clock signals for CPU operation, while the low-frequency circuit generates clock signals for low-speed modes. This segmentation allows independent optimization of each circuit and enables selective operation to reduce overall power dissipation.
2Speed
If a PLL circuit is used to generate high-frequency clock signals from a low-frequency oscillator, then frequency multiplication is achieved, but the PLL and low-frequency oscillator must be provided independently, increasing device complexity
Solution Approach 1:
The high-frequency and low-frequency oscillation circuits are merged into a single integrated oscillator device. Both circuits share common internal structures and control mechanisms, eliminating the need for separate independent PLL and oscillator circuits. This integration reduces device complexity while maintaining the ability to generate both high and low frequency clock signals as needed.
3Adaptability or versatility
If a low-frequency oscillator operates independently to provide sub-clock signals, then low-speed operation is enabled, but the built-in oscillator and low-speed clock oscillator must be provided independently, increasing device complexity
Solution Approach 1:
The oscillator device is designed with multi-functionality, where a single integrated circuit can operate in multiple modes (high-frequency main clock mode and low-frequency sub-clock mode). The same device structure supports both CPU operation and low-speed timer operations, eliminating the need for separate independent oscillator circuits and reducing overall device complexity.
Data Source
AI summary
An oscillator circuit includes a clock oscillator which outputs a main clock signal having an oscillating frequency switched between a high frequency and a low frequency in response to a frequency selection signal, and a frequency divider circuit which outputs a sub-clock signal having a divided frequency equivalent to a frequency division ratio of the oscillating frequency of the main clock signal, the frequency division ratio being switched in response to the frequency selection signal. The divided frequency of the sub-clock signal is predetermined for each of the high frequency and the low frequency to which the oscillating frequency is switched in response to the frequency selection signal.