Switchable Pin Design for Dynamic Off-Chip Bandwidth
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Solution Overview
Problem
Conventional processor designs face limitations in off-chip memory bandwidth, particularly during memory-intensive phases, leading to performance bottlenecks due to static pin allocation, which fails to dynamically adjust to changing workload demands.
Innovation Solution
A switchable pin design that dynamically allocates pins between power delivery and signal transmission modes, using a memory controller to identify memory-intensive phases and switch between multi-bus and single-bus modes, thereby increasing off-chip bandwidth by converting power pins to signal pins or vice versa.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pins are statically allocated for power delivery in conventional processor designs, then power supply stability is ensured, but off-chip memory bandwidth is limited during memory-intensive phases
Solution Approach 1:
The patent implements dynamic pin switching that allows pins to transition between power delivery mode and signal transmission mode based on real-time workload detection. When memory-intensive phases are detected, previously power-dedicated pins are dynamically repurposed as signal pins to expand memory bandwidth, resolving the contradiction between static allocation stability and dynamic adaptability
Solution Approach 2:
The patent makes pins multi-functional by enabling them to serve dual purposes: power delivery during compute-intensive phases and signal transmission during memory-intensive phases. This universality allows the same physical pins to adapt to different functional requirements, increasing off-chip bandwidth without adding dedicated signal pins
2Use of energy by moving object
If processor frequency is scaled down to save power during memory-intensive phases, then energy consumption is reduced, but performance is degraded
Solution Approach 1:
The patent creates additional memory access pathways by repurposing power pins as signal pins, effectively copying the memory interface capability to parallel channels. This allows the processor to maintain higher frequencies during memory-intensive workloads because the expanded bandwidth reduces memory access bottlenecks, thereby avoiding performance degradation while managing power consumption
3Productivity
If additional signal pins are added to increase off-chip bandwidth, then memory bandwidth is improved, but device complexity and power delivery capability are worsened
Solution Approach 1:
Rather than adding permanent signal pins that would increase device complexity, the patent dynamically reconfigures existing power pins to function as signal pins when needed. This temporal multiplexing approach increases bandwidth without permanently increasing pin count or configuration complexity, as the same pins serve different functions at different times
Data Source
AI summary
Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a portion of allocated pins of a processor with switchable pins, connecting the processor to a memory interface configured to switch the switchable pins between a power mode and a signal mode, providing a metric configured to identify which of the power mode and the signal mode is most beneficial during 1 millisecond intervals, and switching the switchable pins to signal mode during intervals where the signal mode provides more benefit than the power mode.