Switchable PLL Clock Handover Using Stored Frequency Difference
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Solution Overview
Problem
Phase locked loops (PLLs) face challenges in minimizing phase changes during switch-over between clock signals with different frequencies, leading to potential data transfer errors and requiring small PLL bandwidths that are difficult to implement, especially when frequencies differ significantly.
Innovation Solution
The implementation of a phase detector that can switch between operating modes to determine and store frequency differences between unused and used clock signals, allowing for immediate oscillator frequency adjustment during switch-over, thereby improving the quality of the PLL output signal without requiring specific PLL bandwidth settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the PLL bandwidth is reduced to minimize phase changes during switch-over, then phase stability is improved, but the capture range deteriorates and implementation becomes difficult
Solution Approach 1:
The patent applies preliminary action by pre-determining and storing the frequency difference between the currently used clock signal and alternative clock signals before switch-over occurs. The phase detector continuously monitors and stores this frequency difference information, so that when a switch-over is needed, the oscillator can immediately apply the stored frequency difference to adjust its output frequency, avoiding the need for slow bandwidth-limited phase adaptation during the actual switch-over event.
2Stability of the object's composition
If the PLL bandwidth is reduced to minimize phase changes during switch-over, then phase stability is improved, but the capture range deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-determining and storing the frequency difference between the currently used clock signal and alternative clock signals before switch-over occurs. The phase detector continuously monitors and stores this frequency difference information, so that when a switch-over is needed, the oscillator can immediately apply the stored frequency difference to adjust its output frequency, avoiding the need for slow bandwidth-limited phase adaptation during the actual switch-over event.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the oscillator's operating frequency based on the stored frequency difference parameter. When a clock signal switch-over is required, the system changes the frequency parameter of the oscillator output by adding the pre-stored frequency difference to the reference frequency, enabling rapid adaptation to new clock signals with different frequencies without being constrained by the PLL bandwidth.
3Speed
If the oscillator frequency is to change immediately during switch-over, then frequency response is improved, but phase changes occur in the output signal
Solution Approach 1:
The patent applies preliminary action by pre-determining and storing the frequency difference between the currently used clock signal and alternative clock signals before switch-over occurs. The phase detector continuously monitors and stores this frequency difference information, so that when a switch-over is needed, the oscillator can immediately apply the stored frequency difference to adjust its output frequency, avoiding the need for slow bandwidth-limited phase adaptation during the actual switch-over event.
Data Source
AI summary
The invention relates to a phase locked loop or “PLL” (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used. The PLL output signal (CKout) can thus follow more quickly any switch-over-related frequency change of the clock signal being used.