Switchable Termination Resistance Circuit for EMI-Robust Transceivers
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Solution Overview
Problem
Existing communication systems face challenges in reducing power consumption and accommodating high electromagnetic interference while maintaining accurate signal transmission in transceivers, particularly in automotive applications where high voltages and fluctuating common mode voltages are prevalent.
Innovation Solution
A switchable termination resistance circuit is implemented using NMOS and PMOS switches, Zener diodes, and a branch diode configuration to connect and disconnect termination resistance dynamically, allowing the circuit to operate efficiently under electromagnetic interference and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the termination resistance is connected at the transmitter side during transmission phases, then signal reflection is reduced, but power consumption increases
Solution Approach 1:
The termination resistance is made dynamically switchable between connected and disconnected states based on transmission phase. During first and second phases when differential voltage is applied, the termination resistance is disconnected to reduce power consumption. During third phase when differential voltage is zero, the termination resistance is connected to reduce reflections, thus dynamically adapting the termination state to operational requirements
2Ease of operation
If MOSFETs are used for switching termination resistance in high voltage applications, then switching capability is improved, but the circuit becomes vulnerable to electromagnetic interference and high common mode voltages
Solution Approach 1:
A branch circuit is introduced as an intermediary protective element connected in parallel with the MOSFET switches. This branch circuit absorbs and dissipates voltage spikes and electromagnetic interference through its components (branch diode, branch NMOS switch, branch PMOS switch), protecting the main switching MOSFETs from damage while allowing them to continue functioning for termination resistance control
3Reliability
If the termination resistance is continuously connected, then reflections are minimized, but power consumption increases during transmission phases
Solution Approach 1:
The termination resistance is periodically connected and disconnected based on the transmission protocol phases. It is disconnected during active transmission phases (first and second phases) to reduce power consumption, and connected during idle phases (third phase) to minimize reflections, creating a periodic switching pattern that balances power consumption and signal integrity requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power consumption and maintains signal integrity by minimizing reflections and voltage fluctuations, enabling efficient operation even under high electromagnetic interference conditions.
Implementation Method 1
a Zener diode having a cathode side connected to the input node and an anode side connected to the midpoint node
Implementation Method 2
a branch comprising a second Zener diode, a branch diode, a branch NMOS switch and a branch PMOS switch in a series connected arrangement between the midpoint node and a ground line
Implementation Method 3
first and second NMOS termination resistance switches having source connections connected together at a midpoint node and gate connections connected to an input node
Data Source
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AI summary
The disclosure relates to a switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit (1101) for a transmission line transceiver (1301), the switchable termination resistance circuit (1101) comprising: first and second terminals (TXP, TXN) for connection to a transmission line (803); first and second NMOS termination resistance switches (Mnsw1, Mnsw2) having source connections connected together at a midpoint node (1103) and gate connections connected to an input node (1104); a first resistor (R1) connected between the first terminal (TXP) and a drain connection of the first NMOS termination resistance switch (Mnsw1); a second resistor (R2) connected between the second terminal (TXN) and a drain connection of the second NMOS termination resistance switch (Mnsw2); a Zener diode (Dz1) having a cathode side connected to the input node (1104) and an anode side connected to the midpoint node (1103); and a branch (1107) comprising a second Zener diode (Dz2), a branch diode (D3), a branch NMOS switch (Mn4) and a branch PMOS switch (Mp7) in a series connected arrangement between the midpoint node (1103) and a ground line (AGND).