Switchable Topology Processor Tile for Phase-Adaptive Computing
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Solution Overview
Problem
Multicore processors with fixed topologies on a die face inefficiencies in communication and computation due to the inability to adapt topologies during different phases of a program's computation, leading to suboptimal performance for various computing tasks.
Innovation Solution
A computational device with multiple processor tiles on a die featuring switchable topologies, where configuration vectors manage the connections between programmable interconnects and interface blocks, allowing the device to dynamically change topologies between phases of computation, optimizing communication and computation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed topology is used for multiple processor tiles, then the device complexity is reduced and ease of manufacture is improved, but the adaptability to different computing tasks deteriorates and communication efficiency is suboptimal
Solution Approach 1:
The patent implements switchable topologies that allow the interconnect structure to dynamically reconfigure between different computational phases. The topology manager selectively activates specific interconnect structures based on the current phase of computation, enabling the system to adapt from a first topology during a first phase to a second topology during a second phase, thereby resolving the contradiction between fixed simplicity and dynamic adaptability
Solution Approach 2:
The interconnect structure is divided into multiple independent interconnect structures, each optimized for specific computational patterns. The topology manager can selectively activate individual interconnect structures or combinations thereof, allowing the system to segment the communication pathways according to the specific requirements of different computational phases without requiring complete reconfiguration of the entire interconnect fabric
2Productivity
If a fixed topology is used for processor tiles, then the manufacturing process is simplified, but the communication efficiency during different computation phases deteriorates
Solution Approach 1:
The patent designs multiple interconnect structures that can serve different computational phases, where each interconnect structure is optimized for specific communication patterns (e.g., mesh for data parallelism, ring for sequential processing). The topology manager acts as a universal controller that routes traffic through appropriate interconnect structures based on the current computational phase, enabling one system to fulfill multiple specialized functions without requiring separate hardware for each computational pattern
Solution Approach 2:
The system changes the topological parameters of the interconnect structure by selectively activating or deactivating specific interconnect structures based on computational phase requirements. This parameter switching allows the physical infrastructure to remain constant while the logical topology changes, optimizing communication efficiency for different computational patterns without adding permanent structural complexity
3Adaptability or versatility
If multiple interconnect structures are provided for switchable topologies, then the adaptability to different computing phases is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple interconnect structures into a single integrated interconnect fabric that can be selectively activated. Rather than manufacturing separate physical interconnect modules, the design combines multiple topology pathways within a unified structure, where the topology manager enables or disables specific pathways based on computational phase requirements. This merging approach maintains manufacturing simplicity while achieving phase-specific optimization through selective activation of combined structures
Data Source
AI summary
Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.