Switched Capacitor Circuit for ADC Capacitance Error Reduction
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Solution Overview
Problem
Conventional switched capacitor circuits in pipelined analog-to-digital conversion circuits face a trade-off between capacitance errors, conversion speed, power consumption, and chip area, leading to reduced accuracy and increased power consumption due to manufacturing variations in capacitor capacitances.
Innovation Solution
The proposed solution involves a switched capacitor circuit with two capacitors, where a differential input signal is applied across one capacitor in the sample period and a reference voltage is applied to the second capacitor in the hold period, using an amplifier to generate an output signal, thereby reducing the impact of capacitance errors and improving conversion accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the capacitance of capacitors is increased to reduce relative error, then manufacturing precision is improved, but conversion speed decreases and power consumption increases
Solution Approach 1:
The switched capacitor circuit is divided into multiple parallel branches, each containing series-connected capacitors. This segmentation allows the total capacitance to be distributed across multiple smaller capacitor units, reducing the relative error impact while maintaining the required time constants without increasing individual capacitor sizes excessively.
Solution Approach 2:
The invention changes the configuration parameters of the capacitor network from a single large capacitor to multiple series-connected capacitors in parallel branches. This parameter change allows the circuit to achieve the same effective capacitance with smaller individual capacitor values, thereby maintaining faster charging/discharging rates and higher conversion speed while reducing relative error through the series configuration.
2Manufacturing precision
If the capacitance of capacitors is increased to reduce relative error, then manufacturing precision is improved, but the exclusively occupied area increases
Solution Approach 1:
The capacitor network is segmented into multiple parallel branches with series-connected capacitors. This segmentation allows the total capacitance requirement to be met using smaller individual capacitor units that can be arranged more efficiently on the chip, reducing the total occupied area compared to a single large capacitor while maintaining the required precision.
Solution Approach 2:
The capacitor configuration parameters are changed from a single large capacitor to multiple smaller series-connected capacitors. This parameter change enables the circuit to achieve the same electrical characteristics with reduced physical footprint, as smaller capacitor units can be packed more densely and efficiently on the chip substrate.
3Manufacturing precision
If the capacitance of capacitors is increased to reduce relative error, then manufacturing precision is improved, but power consumption increases
Solution Approach 1:
The capacitor network is segmented into multiple parallel branches, allowing the charging and discharging operations to be distributed across multiple smaller capacitor units. This segmentation reduces the instantaneous current requirements and power consumption compared to charging a single large capacitor, while still achieving the required precision through the series configuration.
Solution Approach 2:
The capacitor configuration is changed from a single large capacitor to multiple series-connected capacitors with smaller individual capacitance values. This parameter change reduces the power consumption by lowering the instantaneous charge transfer requirements while maintaining the same time constant and precision characteristics through the series combination effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of the analog-to-digital conversion by minimizing the effect of relative errors in capacitance, maintaining high conversion speed and reducing power consumption, while maintaining a compact chip area.
Implementation Method 1
a first capacitor in which, in a first period, a difference voltage of the differential input signal is applied across first and second terminals, and in a second period, the first terminal is coupled to the output terminal of the amplifier and the second terminal is coupled to the input terminal of the amplifier
Implementation Method 2
a second capacitor in which, in the second period, a reference voltage in accordance with the differential input signal is applied to a first terminal, and the second terminal of the first capacitor is coupled to a second terminal of the second capacitor
Implementation Method 3
an amplifier that has an input terminal and an output terminal
Data Source
AI summary
A conversion circuit for converting a differential input signal into an output signal includes an amplifier that has an input terminal and an output terminal; a first capacitor in which, in a first period, a difference voltage of the differential input signal is applied across first and second terminals, and in a second period the first terminal is coupled to the output terminal of the amplifier and the second terminal is coupled to the input terminal of the amplifier; and a second capacitor in which, in the second period, a reference voltage in accordance with the differential input signal is applied to a first terminal, and the second terminal of the first capacitor is coupled to a second terminal of the second capacitor.