Switched-Capacitor Track-and-Hold Circuit for High-Speed ADC Gain
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Solution Overview
Problem
Conventional track-and-hold circuits, particularly in time-interleaved ADCs, face challenges in modern CMOS processes with limited headroom and short channel transistors, making it difficult to achieve sufficient gain for high-speed applications like SerDes links.
Innovation Solution
The proposed track-and-hold circuit employs a configuration with first and second amplifier stages and switched capacitor circuitry, where the switched capacitor circuitry decouples and couples inputs between the stages in track and hold modes, and includes an auxiliary amplifier stage with positive feedback for gain calibration, enabling improved gain and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional track-and-hold circuits are implemented in modern CMOS processes with short channel transistors to meet high-speed requirements, then speed is improved, but gain becomes insufficient
Solution Approach 1:
The amplifier is divided into two separate stages: a main amplifier stage and an auxiliary amplifier stage. The main stage handles the primary amplification function while the auxiliary stage provides additional gain enhancement. This segmentation allows each stage to be optimized independently, enabling the system to achieve both high speed and sufficient gain that cannot be obtained with a single conventional amplifier stage.
2Speed
If modern CMOS processes are used to achieve high-speed operation, then speed is improved, but headroom for analog circuitry is limited
Solution Approach 1:
The switched capacitor circuitry introduces a temporal dimension to the coupling between amplifier stages. By using time-multiplexed switching, the circuit achieves complex functionality without requiring additional static headroom. The capacitors store and transfer signals between stages during different phases of the clock cycle, effectively adding a time-based dimension to the signal path that bypasses the limited voltage headroom constraint.
3Reliability
If switched capacitor circuitry is used to couple amplifier stages in track mode, then decoupling inputs from outputs is achieved, but circuit complexity increases
Solution Approach 1:
The switched capacitor circuitry operates periodically with clock signals, alternating between track mode and hold mode. During track mode, capacitors are connected to the input to track the signal. During hold mode, the same capacitors are switched to hold the sampled value and couple it to the next stage. This periodic switching provides reliable signal isolation and transfer using simple capacitor-switch structures that can be implemented with standard CMOS devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies implementation within the limited headroom of modern CMOS processes, provides substantial gain, and is well-suited for high-speed applications, enhancing performance in time-interleaved ADCs and other ADC types.
Implementation Method 1
switched capacitor circuitry coupled between the first and second amplifier stages... couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via respective first and second capacitors
Data Source
AI summary
A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.