Switched-Capacitor JPEG Compression With Selective ADC Gating
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Solution Overview
Problem
Traditional JPEG compression systems face high power consumption due to the continuous operation of analog-to-digital converters (ADCs) and complex network architectures, which are not suitable for resource-constrained environments, and existing analog solutions lack an end-to-end methodology for converting analog pixel data into JPEG-encoded information bits efficiently.
Innovation Solution
A system utilizing a switch capacitor based analog processing unit that compresses input analog samples in the analog domain, employing a 2D Discrete Cosine Transform (DCT) and quantization using switched capacitor circuitry, followed by selective activation of an ADC for significant samples and power gating for insignificant ones, enabling low-power JPEG compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional digital JPEG compression systems are used with continuous ADC operation, then image compression functionality is achieved, but power consumption becomes excessively high
Solution Approach 1:
The patent segments the image samples into significant and insignificant portions based on human visual system characteristics. Only significant samples requiring compression are processed through the full JPEG pipeline, while insignificant samples are handled differently, reducing overall processing power requirements while maintaining compression functionality.
Solution Approach 2:
The patent applies partial action by selectively activating the ADC and compression processing only when necessary for significant samples. The system performs minimal processing for insignificant samples, avoiding excessive computation and power consumption while still achieving functional compression output.
2Device complexity
If complex network architecture with registers and division blocks is employed, then JPEG compression is achieved, but device area and complexity increase significantly
Solution Approach 1:
The patent extracts and removes unnecessary processing components from the traditional JPEG architecture. By identifying and eliminating redundant registers, division blocks, and processing stages for insignificant samples, the system reduces device area and complexity while preserving essential compression functionality for significant samples.
Solution Approach 2:
The patent applies partial processing action by implementing a simplified processing path for insignificant samples that bypasses complex arithmetic operations. This selective processing reduces the required device area and complexity while maintaining adequate compression performance through the simplified path.
3Measurement precision
If ADC is consistently engaged for all samples, then complete digitization is achieved, but power requirements become substantial
Solution Approach 1:
The patent applies different processing qualities to different regions of the image data based on local characteristics. Significant samples receive full ADC conversion and compression processing for high precision, while insignificant samples receive reduced processing with lower precision requirements, optimizing the balance between measurement precision and power consumption locally across different image regions.
Solution Approach 2:
The patent applies partial digitization by engaging the ADC only for significant samples that require accurate compression representation. Insignificant samples undergo minimal or no ADC conversion, reducing overall ADC power consumption while maintaining adequate measurement precision for the portions of the image that actually require it.
Data Source
AI summary
A system and method for converting direct analog samples to compressed digitized samples is disclosed. The system includes a switch capacitor based analog processing unit configured to receive input analog samples from an image processing system. Further, the switch capacitor based analog processing unit is configured to compress the received plurality of input analog samples in analog domain to generate compressed analog samples using a plurality of switch capacitor circuitry. The compressed analog samples include a plurality of significant analog samples and a plurality of insignificant analog samples. Further, the system includes an analog-to-digital converter (ADC) electrically connected to the switch capacitor based analog processing unit. The ADC is configured to convert the plurality of significant analog samples to a plurality of digitized significant bits. The ADC is activated for processing the plurality of significant analog samples and power gated for the plurality of insignificant analog samples.