Switched-Capacitor ADC Cores for Stochastic Rounding Accuracy
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Solution Overview
Problem
Deep learning systems face challenges in implementing stochastic rounding, which adds complexity and requires additional circuitry for individual unit computes or ensembles, affecting energy consumption and processing efficiency.
Innovation Solution
The use of multiple analog to digital converters configured to produce digital outputs by comparing internal residual voltages, with a switched capacitor computation for determining the least significant bit, allowing for parallel computations and improved processing rates through residual voltage mapping and multiplexing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If stochastic rounding is implemented using additional circuitry for individual unit computes, then rounding accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple ADCs into an ensemble where they share common resources (reference voltages, capacitors, comparators) to perform stochastic rounding. Instead of adding separate circuitry to each ADC, the ADCs are merged into a collaborative system where the ensemble collectively performs the stochastic rounding function, reducing overall device complexity while maintaining rounding accuracy.
Solution Approach 2:
The shared capacitors and reference voltage circuits serve multiple functions: they are used by multiple ADCs in the ensemble for both individual conversions and collective stochastic rounding operations. This multi-functionality reduces the total amount of dedicated circuitry needed compared to having separate stochastic rounding circuitry for each ADC.
2Measurement precision
If stochastic rounding is implemented with additional circuitry, then rounding accuracy is improved, but energy consumption increases
Solution Approach 1:
By merging multiple ADCs into an ensemble that shares power-consuming components (capacitors, reference voltage circuits, comparators), the patent reduces total energy consumption. The shared resources are utilized collectively by all ADCs in the ensemble, so the energy cost of stochastic rounding is amortized across multiple conversions rather than being duplicated for each individual ADC.
Solution Approach 2:
The ADC ensemble performs stochastic rounding using its own internal residual voltages and shared resources without requiring external stochastic rounding circuitry. The system serves its own rounding needs through the collaborative operation of the ADCs, eliminating the need for additional dedicated energy-consuming circuitry.
3Measurement precision
If stochastic rounding is implemented for individual unit computes, then processing accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent segments the stochastic rounding process into discrete phases within the ADC conversion timeline. The residual voltage comparison for stochastic rounding is performed during specific phases (e.g., during the conversion process itself rather than as a separate post-processing step), allowing accuracy to be maintained while minimizing impact on overall processing speed.
Solution Approach 2:
The ADC ensemble maintains continuous operation by processing multiple inputs simultaneously in parallel. While individual ADCs within the ensemble perform stochastic rounding, the overall system maintains high throughput because other ADCs are processing other inputs concurrently, and the ensemble can be configured to output results at high rates through parallel operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and efficiency of stochastic rounding in deep learning systems by reducing power consumption and improving processing speed, while maintaining robust neural network accuracy with limited additional structural complexity.
Implementation Method 1
a switched capacitor digital to analog converter having a plurality of capacitors used for the switched capacitor computation
Implementation Method 2
configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter
Data Source
AI summary
An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.


