Adjustable Switched Capacitor Bias Circuit for Fast Power-Up
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Solution Overview
Problem
DC bias voltage circuits face challenges in achieving rapid power-up without compromising noise performance, particularly in integrated circuit technology, where high resistance values are difficult to implement, leading to uncertain settling times and prolonged manufacturing test times due to the need for low-cut-off frequencies in low-pass filters.
Innovation Solution
A DC bias voltage circuit with an adjustable switched capacitor resistor low-pass filter, controlled by a clock signal frequency, allows for precise setting of the cut-off frequency, enabling rapid power-up and effective noise suppression by switching between high and low clock frequencies during power-up and normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a low-pass filter with very low cut-off frequency is used to reduce noise, then noise performance is improved, but power-up time becomes excessively long
Solution Approach 1:
The patent applies dynamics by making the cut-off frequency of the low-pass filter variable rather than fixed. The filter transitions from a high cut-off frequency during power-up (enabling fast settling) to a low cut-off frequency during normal operation (enabling noise suppression). This dynamic adjustment resolves the contradiction between fast power-up and low noise performance.
Solution Approach 2:
The patent uses periodic action through two distinct operational phases: a power-up phase with high cut-off frequency and a normal operation phase with low cut-off frequency. The system periodically switches between these states, using the high-frequency phase only during the transient power-up period and the low-frequency phase during sustained operation to achieve both fast settling and low noise.
2Object-affected harmful factors
If a high resistance value is used in the low-pass filter to achieve low cut-off frequency, then noise filtering is improved, but die area consumption increases unacceptably
Solution Approach 1:
The patent replaces the mechanical/physical resistor with a switched-capacitor circuit that simulates high resistance through switching action. Instead of using a physical resistor with GΩ-range resistance that would occupy large die area, the invention uses capacitors and switches controlled by a clock signal to create an equivalent high resistance effect with minimal area consumption.
Solution Approach 2:
The patent changes the resistance parameter dynamically by using a switched-capacitor configuration where the effective resistance is determined by the clock frequency and capacitor values rather than a fixed physical resistor. This allows achieving extremely high effective resistance values (several GΩ or tens of GΩ) without the area penalty of physical high-value resistors.
3Area of stationary object
If non-linear devices are used to replace high value resistors, then die area is reduced, but power-up time becomes ill-defined and uncertain
Solution Approach 1:
The patent applies dynamics by using a switched-capacitor circuit with controlled switching behavior that provides predictable and stable timing characteristics. Unlike non-linear devices whose resistance varies with temperature and bias conditions, the switched-capacitor implementation provides a well-defined time constant determined by the clock frequency and capacitor values, enabling accurate power-up time estimation.
Solution Approach 2:
The patent incorporates feedback through the clock signal that controls the switching of the capacitor. The regular periodic switching provides a stable reference for timing, allowing the system to predict and control the power-up settling time accurately. The feedback mechanism ensures that the effective resistance remains stable and predictable throughout operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables rapid power-up of the DC bias voltage circuit with well-defined settling times across temperature and semiconductor process variations, while maintaining low noise performance and reducing die area consumption, suitable for integrated circuit implementation.
Implementation Method 1
a RC based low-pass filter have been coupled to an output of a charge pump stage to attenuate noise at the output thereof
Implementation Method 2
The low-pass filter comprises an adjustable switched capacitor resistor setting a cut-off frequency of the low-pass filter
Data Source
AI summary
The present invention relates to a DC bias voltage circuit comprising a DC bias voltage generator adapted to supply a first DC voltage. A low-pass filter has an input operatively coupled to the first DC voltage to produce a second DC voltage at a low-pass filter output. The low-pass filter comprises an adjustable switched capacitor resistor setting a cut-off frequency of the low-pass filter and a controller is adapted to controlling a resistance of the adjustable switched capacitor resistor.