Switched Capacitor MOSFET Layout for Charge Injection Cancellation
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Solution Overview
Problem
Existing switched capacitor circuits face challenges in effectively canceling charge injection and clock feedthrough, particularly in small or minimum sized MOS switches, due to incomplete charge cancellation and process variations.
Innovation Solution
The proposed switched capacitor circuit addresses charge injection and clock feedthrough by connecting the source and drain terminals of the switch MOS to a common terminal through known impedances, ensuring matched impedance between the nodes to achieve complete charge cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single MOS switch is used in compact designs, then device area is reduced, but charge injection and clock feedthrough errors increase
Solution Approach 1:
The patent introduces a dummy MOS switch as an intermediary element that absorbs the harmful charge injection and clock feedthrough effects. The dummy switch is sized to match the impedance of the signal path, allowing it to act as a mediator that captures the injected charge and prevents it from corrupting the analog signal, thereby enabling compact single-switch designs to maintain high accuracy
Solution Approach 2:
The patent modifies the parameters of the dummy MOS switch, specifically its width, to match the impedance characteristics of the signal path. By adjusting the dummy switch width to be equal to the signal switch width, the impedance matching ensures optimal charge absorption and cancellation of clock feedthrough effects, resolving the accuracy issue in compact designs
2Measurement precision
If complementary MOSFETs are used to cancel charge injection, then charge cancellation is improved, but process variations cause incomplete cancellation
Solution Approach 1:
The patent changes the parameter of the dummy MOS switch width to match the signal switch width, ensuring impedance matching. This parameter adjustment makes the charge absorption capability dependent on impedance rather than on precise matching of transistor characteristics, thereby overcoming the reliability issues caused by process variations in complementary MOSFET approaches
3Object-generated harmful factors
If dummy MOS is used to absorb injected charge, then charge injection is reduced, but impedance matching is difficult to achieve
Solution Approach 1:
The patent simplifies the impedance matching process by providing explicit guidance on setting the dummy MOS width equal to the signal MOS width. This straightforward parameter relationship eliminates the need for complex impedance calculation and adjustment procedures, making it easy to achieve optimal charge absorption while maintaining simple device design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively cancels charge injection and clock feedthrough, reducing errors in analog signals and improving the accuracy of switched capacitor circuits, especially in compact designs with small MOS switches.
Implementation Method 1
Charge injection occurs when the switch MOS is turned off, injecting its residual channel charge into its source and drain terminals
Implementation Method 2
Clock feedthrough is an undesired capacitive coupling between the digital signal connected to the gate of the switch MOS and the analog signal at the source or drain of the switch MOS caused by its gate-source/gate-drain capacitance
Data Source
AI summary
A switched capacitor circuit, including a metal-oxide-semiconductor field-effect transistor-based switch comprising: a first metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to a first node and the drain is connected to a second node or wherein the drain is connected to the first node and the source is connected to the second node; a second metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to the drain and the source and the drain are together connected to the second node; a first capacitor connected between the first node and a third node; and a second capacitor connected between the second node and the third node.