Switched-Capacitor Charge Pump for eDRAM Power Management
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Solution Overview
Problem
Conventional charge pump designs for embedded dynamic random-access memory (eDRAM) suffer from inefficiencies related to capacitive loading, voltage ripples, and peak current density, which affect power management in demanding applications.
Innovation Solution
A switched-capacitor charge pump with an enhanced two-phase topology, utilizing first and second switched capacitors, cross-coupled transistors, and a pump output connected to the source terminals of these transistors, along with non-overlapping wide and narrow clock signals for efficient clock edge handling and reduced clock loading, is developed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional charge pump designs are used for eDRAM, then the memory array can be powered, but inefficiencies occur related to capacitive loading, voltage ripples, and peak current density
Solution Approach 1:
The charge pump is divided into multiple independent pumping cells (first charge pump cell, second charge pump cell) that operate in alternating phases. Each cell contains switched capacitors and transistors configured to pump charge independently, allowing one cell to charge while the other discharges, thereby reducing voltage ripples and improving power efficiency by distributing the capacitive loading across multiple stages rather than a single stage.
Solution Approach 2:
The charge pump employs periodic two-phase non-overlapping clock signals to alternately control the switching of capacitors in each pumping cell. During the first phase, the first cell charges capacitors while the second cell discharges; during the second phase, the roles reverse. This periodic alternating action smooths current draw, reduces peak current density, and maintains more stable output voltages compared to single-phase operation.
2Area of stationary object
If deep-trench capacitors are used to reduce footprint, then area is reduced, but power management becomes more challenging
Solution Approach 1:
The charge pump circuit parameters (capacitor values, transistor sizing, clock frequency) are optimized to match the specific electrical characteristics of deep-trench capacitors. By adjusting these parameters, the circuit achieves efficient charge pumping with minimal power loss, compensating for the higher density packaging of deep-trench capacitors and reducing overall power consumption despite the area reduction.
3Power
If switched capacitors are charged and discharged during clock phases, then voltage multiplication is achieved, but clock loading and switching noise increase
Solution Approach 1:
The switching noise and clock loading are segmented across multiple pumping cells operating in parallel with non-overlapping clock phases. Each cell handles a portion of the total charge pumping task, distributing the switching activity in time and space. This segmentation reduces the instantaneous current spikes and electromagnetic noise associated with single-stage switching, while still achieving the required voltage multiplication at the output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves more efficient energy conversion with improved active and standby power control, providing a compact design that reduces inefficiencies and enhances power management in eDRAM systems.
Implementation Method 1
first and second switched capacitors (62, 64)
Implementation Method 2
first and second cross-coupled transistors (76, 78) connected to second nodes of the switched capacitors
Data Source
AI summary
A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.