Switched Capacitor Clock Suppression for Supply Droop Noise

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Solution Overview

Problem

Switched capacitor circuits face noise issues due to supply droop during binary output signal transitions, which affect the accuracy of signal processing, especially in integrated circuits where noise reduction is crucial.

Innovation Solution

The system clock signal is temporarily suppressed during 0-1 and/or 1-0 transitions of the binary output signal to prevent noise introduction from supply voltage fluctuations, achieved through a suppression circuitry in the system clock generator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the system clock signal is continuously supplied to the switched capacitor assembly, then the signal processing operates continuously with high productivity, but noise is introduced due to supply droop during binary output signal transitions

Engineering Contradiction:

Improvecontinuous signal processingVSAvoidnoise from supply droop

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The system clock signal is suppressed periodically during binary output signal transitions (0-1 and/or 1-0 transitions) to prevent supply droop noise. The suppression circuitry temporarily interrupts the clock signal at these specific moments, allowing the supply voltage to stabilize before resuming normal signal processing operations.

Inventive Principle:

Principle #19Periodic action

2Object-affected harmful factors

If the system clock signal is suppressed during binary output transitions, then noise is reduced by stabilizing supply voltage, but signal processing is interrupted temporarily

Engineering Contradiction:

Improvenoise reductionVSAvoidinterruption of signal processing

Core Design Contradiction:

Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The clock signal suppression is applied partially - only during the specific moments when binary output transitions occur (0-1 and/or 1-0 transitions). This targeted approach suppresses noise at critical moments while minimizing the overall interruption time, allowing signal processing to resume immediately after the transition period.

Inventive Principle:

Principle #16Partial or excessive action

3Measurement precision

If high accuracy signal processing is required, then noise reduction measures are implemented, but the circuit complexity increases due to suppression circuitry

Engineering Contradiction:

Improvesignal accuracyVSAvoidsuppression circuitry

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The suppression circuitry is integrated into the existing system clock generator that already provides clock signals to the switched capacitor assembly. By merging the noise suppression function with the existing clock generation infrastructure, the additional complexity is minimized while achieving the desired noise reduction for high accuracy signal processing.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7629837B2Noise reduction for switched capacitor assemblies

Publication Date: 2009.12.08 SENSIRION HLDG

AI summary

An integrated circuit comprises an assembly of switched capacitors operated under control of a system clock signal. It further comprises a signal driver for generating a binary output signal at an output pad. The system clock signal is suppressed for a certain time period after each transition of the output signal, thereby preventing voltage droop generated by the transition to introduce noise in the signals of the assembly of switched capacitors.