Switched-Capacitor DC-to-DC Converter Vertical Stacking
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Solution Overview
Problem
Switched-inductor converters occupy large areas, limiting their use in compact systems, while switched-capacitor converters, suitable for low power and compact size, face limitations in increasing capacitance due to area constraints when integrating switching elements and capacitors in a single chip.
Innovation Solution
A method for fabricating a switched-capacitor DC-to-DC converter involves forming switching elements and interconnection patterns on a semiconductor layer, followed by the formation of capacitors that vertically overlap with the logic structure, increasing capacitance per unit area without requiring complex through-silicon via techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If switching elements and capacitors are integrated in a single chip, then device compactness is improved, but capacitance value is limited due to area constraints
Solution Approach 1:
The patent transitions from planar capacitor layout to three-dimensional vertical stacking, where capacitors are formed in multiple layers above the semiconductor substrate. This dimensional change allows capacitance to increase vertically rather than being constrained by horizontal chip area, resolving the contradiction between compact integration and capacitance value.
Solution Approach 2:
The patent implements nested structures where capacitors are embedded within and around the logic structure. Multiple capacitor layers are positioned at different heights, with some capacitors nested within the vertical space occupied by the logic structure, maximizing space utilization and achieving high capacitance in a compact footprint.
2Quantity of substance
If capacitor area is increased to achieve higher capacitance, then capacitance value is improved, but device compactness deteriorates
Solution Approach 1:
The patent resolves this contradiction by moving capacitor placement from the two-dimensional plane to three-dimensional space. Capacitors are formed in vertical stacks with multiple electrodes and dielectric layers positioned at different heights, allowing high capacitance values to be achieved without increasing the horizontal chip footprint.
Solution Approach 2:
The patent merges the logic structure and capacitor structure into a single integrated three-dimensional assembly. The capacitors are positioned to vertically overlap with the logic structure, combining what were traditionally separate functional blocks into a compact unified structure that achieves high capacitance without additional area.
3Quantity of substance
If through-silicon via techniques are used to increase capacitance, then capacitance value is improved, but device complexity increases
Solution Approach 1:
The patent extracts the capacitor formation process from the complex through-silicon via fabrication sequence. Capacitors are formed as separate structural elements using standard semiconductor processing steps, independent of the via formation processes, thereby increasing capacitance without adding fabrication complexity.
Solution Approach 2:
The patent performs preliminary capacitor structure formation during the standard logic structure fabrication process, before final interconnection layers are added. This preliminary action integrates capacitor formation into the existing fabrication flow without requiring additional complex processing steps or specialized techniques.
Data Source
AI summary
A method of fabricating a switched-capacitor converter includes providing a semiconductor layer having a top surface and a bottom surface, forming switching elements on the top surface of the semiconductor layer, forming a first insulation layer and first interconnection patterns on the switching elements, forming a second insulation layer over the first insulation layer and the first interconnection patterns, forming a second interconnection pattern over the second insulation layer, forming a third insulation layer over the second insulation layer and the second interconnection pattern, forming third interconnection patterns and a lower interconnection pattern over the bottom surface of the semiconductor layer, forming a capacitor over the lower interconnection pattern, forming a fourth insulation layer over the bottom surface of the semiconductor layer to expose an upper electrode pattern of the capacitor, forming a fifth insulation layer covering the capacitor, and forming pads in the fifth insulation layer.