Switched-Capacitor DC-to-DC Converter Vertical Capacitor Stacking
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Solution Overview
Problem
Switched-capacitor DC-to-DC converters face challenges in integrating high capacitance values and CMOS circuits within a single chip due to the compact size requirements of mobile systems, leading to capacitors being positioned outside the semiconductor chip.
Innovation Solution
A switched-capacitor DC-to-DC converter design incorporating a first and second P-channel MOS transistor, a first and second N-channel MOS transistor, and a capacitor with a multi-layered structure, where the capacitors are vertically stacked to increase integration density and reduce the planar area occupied, allowing for higher capacitance values to be integrated within the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a capacitor having a high capacitance value is integrated in a single chip with CMOS circuit, then integration density is improved, but it becomes difficult to achieve due to area constraints
Solution Approach 1:
The patent transitions from planar capacitor layout to three-dimensional vertical stacking. Multiple capacitor layers are stacked vertically above each other, utilizing the vertical dimension to increase capacitance without expanding the horizontal chip footprint. This dimensional change allows high capacitance values to be achieved within compact area constraints.
Solution Approach 2:
The patent implements nested capacitor structures where conductive patterns and dielectric layers are arranged in overlapping configurations. Inner capacitor elements are positioned within the vertical projection area of outer elements, creating a nested arrangement that maximizes capacitance density within the available planar space.
2Quantity of substance
If capacitor is positioned outside semiconductor chip, then high capacitance value can be achieved, but integration density deteriorates
Solution Approach 1:
The patent moves capacitor integration from external positioning to internal integration by utilizing the vertical dimension through multi-layer stacking. This allows high capacitance values to be achieved within the chip boundaries, eliminating the need for external capacitor placement and improving overall integration density.
3Adaptability or versatility
If inductor is used in switched-inductor converter, then wide operating range and high efficiency are achieved, but area occupied increases
Solution Approach 1:
The patent extracts the energy storage function from inductors and implements it using capacitors in a switched-capacitor converter architecture. By removing the inductor component entirely and replacing it with capacitor-based energy transfer mechanisms, the design achieves compact area occupation while maintaining converter functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient conversion of DC voltage levels while increasing integration density and reducing the size of the converter, making it suitable for compact systems by effectively utilizing the available space within the semiconductor chip.
Implementation Method 1
The capacitor is coupled between the first node and the second node. The capacitor includes a first capacitor and a second capacitor.
Data Source
AI summary
A switched-capacitor DC-to-DC converter includes a first P-channel MOS transistor, a first N-channel MOS transistor, a second P-channel MOS transistor, and a second N-channel MOS transistor which are connected in series. Drain terminals of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other through a first node, and drain terminals of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other through a second node. A capacitor is coupled between the first and second nodes. The capacitor includes a first capacitor and a second capacitor which are coupled in parallel between the first and second nodes.