Switched-Capacitor Multi-Level DAC for Improved Linearity
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Solution Overview
Problem
Multi-bit sigma-delta analog-to-digital converters face limitations in linearity due to capacitor mismatch and reference voltage variations in their digital-to-analog converters (DACs), which affect signal-to-noise and distortion ratio (SNDR) performance, especially at lower oversampling rates.
Innovation Solution
A method and system that map uniformly distributed input codes to non-uniformly distributed codes in a switched capacitor DAC, using a charge accumulator and multiple reference voltages to ensure each capacitor provides a proportional nominal charge, reducing the impact of capacitor mismatch and reference voltage variations, thereby improving linearity and SNDR performance without the need for dynamic element matching or calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-bit quantizer and multi-bit DAC are used instead of single-bit, then the oversampling ratio can be reduced, but the linearity performance deteriorates due to capacitor mismatch and reference voltage variations
Solution Approach 1:
The patent applies asymmetry by using different capacitor values in the DAC structure. Specifically, it employs a first capacitor with a first value and a second capacitor with a second value that is different from the first value. This asymmetric capacitor configuration helps compensate for mismatch effects and improves linearity performance while maintaining the benefits of multi-bit operation at lower oversampling ratios.
Solution Approach 2:
The patent changes the parameter values of capacitors to optimize performance. By selecting specific capacitor values (first value and second value that differs), the system achieves better linearity. The method also involves changing the operating parameters by using specific switching sequences and charge transfer ratios to compensate for non-ideal effects in the multi-bit DAC.
2Manufacturing precision
If foreground calibration or background calibration techniques are used to improve DAC linearity, then linearity performance improves, but device complexity increases
Solution Approach 1:
The patent implements self-service by designing a DAC structure that automatically compensates for its own non-ideal characteristics without requiring external calibration circuits or additional control logic. The asymmetric capacitor configuration and charge transfer method inherently correct for mismatch and reference voltage variations, eliminating the need for foreground or background calibration techniques and thereby reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces non-linear effects, achieving higher linearity and SNDR performance at lower oversampling rates, allowing for more DAC levels with fewer capacitors and reference voltages, and can be implemented in various data converter systems like sigma-delta modulators.
Implementation Method 1
transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator
Data Source
AI summary
In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.