Switched-Capacitor Integrator for Low-Power Double Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional double-sampling sigma-delta modulators face challenges with high power consumption and sensitivity to quantizer input offset due to the need for large transconductance amplifiers to handle both continuous-time and discrete-time inputs, which affects performance and efficiency.
Innovation Solution
A double-sampling integrator system with a switched-capacitor feedback circuit and a control module that generates switching signals based on clock phases and feedback signal polarity to optimize sampling and integration phases, reducing the need for high transconductance amplifiers and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large transconductance amplifiers are used to handle both continuous-time and discrete-time inputs in a double-sampling integrator system, then the system can process both input types effectively, but power consumption increases significantly
Solution Approach 1:
The patent divides the sampling process into two separate sampling circuits: a first sampling circuit for continuous-time inputs and a second sampling circuit for discrete-time inputs. Each sampling circuit operates during different clock phases, allowing the use of smaller transconductance amplifiers since they only need to handle one input type at a time, thereby reducing power consumption while maintaining performance
Solution Approach 2:
The patent implements periodic switching between two sampling circuits using non-overlapping clock phases. The first sampling circuit is active during one phase while the second is inactive, then they switch roles in the next phase. This periodic action allows each amplifier to be optimized for lower power consumption since it only needs to handle one input type at a time
2Productivity
If conventional double-sampling integrator systems are used with both continuous-time and discrete-time inputs, then improved bandwidth and power consumption are achieved compared to single-sampling, but sensitivity to quantizer input offset increases due to residual charge on capacitors
Solution Approach 1:
The patent extracts the residual charge from the capacitors at the end of each sampling phase by using a second sampling circuit to sample the same input during the next clock phase. This extraction of residual charge prevents it from affecting the quantizer input offset, thereby reducing sensitivity while maintaining the bandwidth benefits of double-sampling
Solution Approach 2:
The patent implements a feedback mechanism where the output of the first sampling circuit is fed into the second sampling circuit in the next clock phase. This feedback approach ensures that any residual charge or offset from the first sampling is compensated for in the second sampling, reducing the overall sensitivity to quantizer input offset
Data Source
AI summary
Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.