Switched-Capacitor Calibration for Pole-Zero Doublet Errors
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Solution Overview
Problem
Switched capacitor biasing in analog circuitry causes pole-zero (PZ) doublet errors, leading to signal distortion and slow settling times, which are problematic for high precision systems like oscilloscopes and communication transceivers.
Innovation Solution
A switched capacitor (SC) pole-zero doublet error mitigation system is introduced, which includes logic circuitry coupled to the analog to digital converter (ADC) to compute error mitigation codes that calibrate the SC circuitry, reducing PZ-doublet errors by applying a step function and adjusting resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If switched capacitor biasing circuitry is used in analog circuitry, then good isolation between signal and biasing circuitry is achieved and implementation is simplified, but pole-zero doublet errors are introduced causing signal distortion and slow settling times
Solution Approach 1:
The patent measures the PZ doublet errors generated by the SC biasing circuitry and uses these same errors to generate calibration codes that compensate for the distortion. The harmful PZ doublet artifacts are converted into useful calibration data that, when applied through the capacitor array, cancel out the original errors and improve settling time accuracy.
2Ease of manufacture
If switched capacitor biasing circuitry is used in analog circuitry, then good isolation between signal and biasing circuitry is achieved, but slow settling times are introduced
Solution Approach 1:
The patent measures the slow settling behavior caused by PZ doublet errors and uses this measurement to generate calibration codes. These codes adjust the capacitor array to compensate for the slow settling, converting the timing artifact into useful calibration information that improves the settling time characteristic.
Solution Approach 2:
The patent employs a feedback mechanism where the output of the analog circuitry is measured to detect PZ doublet errors, and this measurement is used to generate calibration codes that are applied back to the SC biasing circuitry through the capacitor array, creating a closed-loop system that actively compensates for settling time issues.
3Manufacturing precision
If logic circuitry is added to compute error mitigation codes, then PZ doublet errors are reduced, but device complexity increases
Solution Approach 1:
The patent uses an existing ADC in the signal chain to perform dual functions: its original conversion function and the additional function of measuring PZ doublet errors for calibration. This multi-functional approach allows error mitigation without adding dedicated measurement hardware, reducing the net increase in device complexity.
Solution Approach 2:
The patent combines the error measurement and calibration code generation functions with the existing ADC and logic circuitry in the signal processing chain. By merging these calibration functions with existing components rather than adding completely separate systems, the patent reduces the overall complexity increase while still achieving PZ doublet error mitigation.
Data Source
AI summary
Examples describe a switched capacitor (SC) circuitry calibrated to mitigate the pole-zero (PZ) doublet errors that occur in an analog circuitry. Due to PZ-doublet errors, the slow settling time response of an input step function to an analog circuitry make it impractical to use in applications such as a digital oscilloscope. Mitigating the PZ-doublet errors in the frequency domain is not practical due to the problem of the generation of low frequency sinusoidal tones. The solution disclosed in the present invention is to apply a step function and examine the output's slow settling error waveform. A signal is input to an analog to digital converter, and the output of the converter is processed by a computation that produces calibration codes. Calibration codes are coupled to a SC circuitry to mitigate the PZ-doublet errors. The error waveform is then minimized within a specified accuracy.