Switched-Capacitor Gain Amplifier for Higher Input Impedance

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Solution Overview

Problem

Switched-capacitance gain amplifiers have low input impedance, which results in high thermal noise, making it challenging to interface with high source impedance sensors while maintaining the same gain and noise floor as standard solutions.

Innovation Solution

The implementation of a switched-capacitance gain amplifier with additional switches and phase-shifted clock signals to improve input impedance, allowing for reduced input current and increased capacitance without degrading noise performance, enabling better interfacing with high source impedance sensors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If switched capacitor network is used in gain amplifier, then gain and noise floor are maintained, but input impedance becomes low

Engineering Contradiction:
Improvenoise floorVSAvoidinput impedance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamic switching of capacitor connections using multiple clock phases (Φ1, Φ2, Φ3, Φ4) to change the effective input impedance over time. By dynamically reconfiguring which capacitors are connected to which inputs during different phases of the clock cycle, the circuit achieves a higher average input impedance while maintaining the same noise floor and gain characteristics.

Inventive Principle:
Principle #15Dynamics

2Object-affected harmful factors

If capacitance is reduced to improve input impedance, then input impedance increases, but thermal noise increases

Engineering Contradiction:
Improveinput impedanceVSAvoidthermal noise
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent employs periodic switching action with four distinct clock phases to repeatedly connect and disconnect different capacitor networks to the inputs. This periodic reconfiguration allows the circuit to maintain a higher effective input impedance over the complete cycle while the noise performance is determined by the total capacitance integrated over all phases, thereby decoupling the impedance-noise tradeoff.

Inventive Principle:
Principle #19Periodic action

3Object-affected harmful factors

If additional switches and phase-shifted clock signals are added, then input impedance improves, but device complexity increases

Engineering Contradiction:
Improveinput impedanceVSAvoidswitching network
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the switched capacitor network into multiple independent capacitor groups (first, second, third, and fourth capacitors) that are switched independently during different clock phases. This segmentation allows each capacitor to be controlled by specific switch combinations, enabling complex impedance transformation through simpler, modular switch-capsitor units rather than requiring a single complex switching mechanism.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP2656500B1Switched-capacitance gain amplifier with improved input impedance
Publication Date: 2015.02.18 MICROCHIP TECHNOLOGY INC
  • EP2656500B1 patent drawingFigure 1~2
  • EP2656500B1 patent drawingFigure 3
  • EP2656500B1 patent drawingFigure 4~5

AI summary

A gain amplifier may have a differential amplifier with feedback capacitors; a switched input stage having a first and second output coupled with the differential amplifier, and having: first and second capacitors, a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches controlled by a first clock signal to connect the first terminals of the first capacitor with the first or second input, respectively and to connect the first terminals of the second capacitors with the second and first input, respectively; and a second plurality of switches controlled by a phase shifted clock signal to connect the second terminal of the first capacitor with a first or second input of the differential amplifier and connecting the second terminal of the second capacitor with the second or first input of the differential amplifier.