Switched Capacitor DC-DC Converter In-Rush Current Control

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Solution Overview

Problem

Switched capacitor DC/DC converters face challenges with high in-rush currents during start-up, which can exceed safe operating limits for FETs, and lack effective fault detection and protection mechanisms, particularly in the absence of inductors to limit current and prevent system damage.

Innovation Solution

A switch controller circuit is integrated within the same package as a current limit circuit and fault detection circuit, using a series FET to control the in-rush current and detect faults during start-up and steady-state operations, with timers and threshold voltage monitoring to manage in-rush currents and output voltage stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the input voltage is directly connected to the capacitors in a switched capacitor converter, then the converter can operate with simple circuit topology, but the in-rush current during start-up can exceed safe operating limits for FETs

Engineering Contradiction:
Improvecircuit topologyVSAvoidFET safe operating current
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A current limit circuit with a series FET is introduced as an intermediary component between the input voltage source and the capacitor network. This additional FET acts as a mediator that controls and limits the in-rush current during start-up, preventing excessive current from damaging other FETs in the switched capacitor converter while maintaining relatively simple overall circuit topology.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If no inductor is used in the switched capacitor circuit to limit current, then the circuit maintains its simple switched capacitor topology, but the in-rush current can rise quickly to very high levels causing FET failure and system damage

Engineering Contradiction:
Improvecircuit topologyVSAvoidin-rush current damage
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the traditional inductor-based current limiting approach with an electronic control mechanism using a series FET and current limit circuit. Instead of relying on the magnetic properties of an inductor to naturally limit current, the system uses active electronic control through the series FET to achieve current limiting, maintaining the simple switched capacitor topology while effectively preventing in-rush current damage.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If fault detection and protection circuits are added to the switched capacitor converter, then system reliability and safety are improved, but the device complexity increases

Engineering Contradiction:
Improvesystem safetyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fault detection and protection functions are merged into the existing current limit circuit and controller package. The same controller that manages the switched capacitor converter operation also performs fault detection, and the series FET used for current limiting also serves as the protection FET. This integration approach improves system reliability and safety while minimizing the increase in device complexity by utilizing existing components for multiple functions.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP2897270B1Switched capacitor DC-DC converter with reduced in-rush current and fault protection
Publication Date: 2018.07.04 LINEAR TECHNOLOGY CORP
  • EP2897270B1 patent drawingFigure 1~3
  • EP2897270B1 patent drawingFigure 4~5
  • EP2897270B1 patent drawingFigure 6

AI summary

To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.