Switched Capacitor Integrator Circuit for Hall Sensor Offset Cancellation
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Solution Overview
Problem
Hall sensors used for magnetic field or current sensing face significant offset errors due to the large area and high power consumption of signal chains with dual integrators, and the low input resistance of reference resistor networks complicates multiplexing and testing.
Innovation Solution
A dual integrator system with a switching network that alternates between two integrators for holding, resetting, and integrating signals, incorporating switched capacitor modules and feedback loops to reduce parasitic and transient errors, and eliminating the reference resistor network by integrating a fraction of the reference voltage in each operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two integrators are used in parallel to enable faster Hall sensor spinning, then the spinning speed is improved, but the area and power consumption increase significantly
Solution Approach 1:
The single integrator is segmented into two operational modes achieved through switching networks: a first mode for integrating the Hall sensor output signal, and a second mode for resetting the integrator and integrating a reference voltage. This temporal segmentation allows one integrator to serve dual purposes, eliminating the need for two parallel integrators while maintaining the required spinning speed.
Solution Approach 2:
The integrator operates in periodic cycles, alternating between the first mode (signal integration) and second mode (reset and reference integration). The switching network periodically transitions the integrator between these modes, enabling fast spinning by ensuring the integrator is ready to integrate the next sensor signal immediately after completing the previous integration and reset cycle.
2Speed
If two integrators are used in parallel to enable faster Hall sensor spinning, then the spinning speed is improved, but the power consumption increases significantly
Solution Approach 1:
The single integrator is segmented into two operational modes achieved through switching networks: a first mode for integrating the Hall sensor output signal, and a second mode for resetting the integrator and integrating a reference voltage. This temporal segmentation allows one integrator to serve dual purposes, eliminating the need for two parallel integrators while maintaining the required spinning speed.
Solution Approach 2:
The integrator operates in periodic cycles, alternating between the first mode (signal integration) and second mode (reset and reference integration). The switching network periodically transitions the integrator between these modes, enabling fast spinning by ensuring the integrator is ready to integrate the next sensor signal immediately after completing the previous integration and reset cycle.
3Stability of the object's composition
If a reference resistor network is used to provide reference voltage, then the reference voltage is stabilized, but the input resistance becomes low making multiplexing and testing difficult
Solution Approach 1:
The reference resistor network is extracted and replaced with a capacitor-based reference voltage integration approach. The integrator directly integrates a reference voltage during the second operational mode, eliminating the need for a physical resistor network at the reference input. This increases the input impedance and enables multiplexing of the reference pin for testing purposes.
Solution Approach 2:
The resistive reference voltage stabilization mechanism is replaced with a capacitive integration mechanism. Instead of using resistors to establish a stable reference voltage, the integrator uses its inherent integration function to average the reference voltage over time, substituting a dynamic capacitive process for a static resistive network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area and power consumption of the semiconductor die, increases input impedance for the reference voltage, and simplifies testing by eliminating the need for low impedance drives, while maintaining accurate signal processing.
Implementation Method 1
a first sampling capacitor and a second sampling capacitor
Implementation Method 2
a first feedback capacitor coupled between the second switch and the negative output, a second feedback capacitor coupled between the fourth switch and the positive output
Data Source
AI summary
A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.