Switched-Capacitor Buffer for Line Receiver Biasing
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Solution Overview
Problem
Conventional line receivers with small transistors face challenges in handling voltage stresses, leading to design trade-offs between linearity, bandwidth, and power consumption, as they struggle to provide desired linearity without sacrificing bandwidth or increasing power consumption.
Innovation Solution
A line receiver design utilizing a switched capacitor circuit coupled with a source-follower buffer, which biases the transistors in a linear region, allowing for efficient signal processing without compromising bandwidth or power consumption, using a capacitive element charged to a DC reference voltage and controlled by switches to manage voltage and power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional line receivers use small transistors to reduce device size, then device complexity is reduced, but linearity deteriorates due to inability to handle voltage stresses
Solution Approach 1:
The patent applies dynamics by using a switched capacitor circuit that alternates between charging and discharging phases, dynamically adjusting the bias voltage applied to the transistor gates. This dynamic biasing allows small transistors to operate in their linear region during signal processing phases, resolving the contradiction between small device size and adequate linearity performance.
Solution Approach 2:
The invention changes the parameter of gate voltage by using a switched capacitor to provide time-varying DC bias voltages to the transistor gates. By controlling the charge/discharge cycles of the capacitor, the bias point is dynamically adjusted to maintain optimal linearity operation for small transistors, thereby improving linearity without increasing device size.
2Manufacturing precision
If conventional line receivers increase power consumption to improve linearity, then linearity is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action through the switched capacitor circuit that operates in alternating phases: charging the capacitor during one phase and discharging it to update the bias voltage during another phase. This periodic operation allows the circuit to maintain transistor bias points for optimal linearity while consuming power only during the switching phases, rather than continuously, thus achieving good linearity with reduced overall power consumption.
Solution Approach 2:
The switched capacitor circuit serves itself by using the signal power and available voltage rails to charge and discharge the capacitor, maintaining the bias conditions without requiring additional continuous power expenditure. The capacitor naturally holds the charge between switching events, providing self-maintained bias conditions that improve linearity without proportionally increasing power consumption.
3Manufacturing precision
If conventional line receivers use active devices to maintain signal quality, then linearity is improved, but power consumption increases
Solution Approach 1:
The patent extracts the biasing function from continuous active device operation and implements it through a switched capacitor circuit. By taking out the continuous power consumption aspect and replacing it with periodic capacitive charging/discharging, the circuit maintains signal quality through proper biasing while dramatically reducing the power required for maintaining those bias conditions compared to continuously active devices.
Solution Approach 2:
The invention substitutes the mechanical/electrical continuous operation of active biasing devices with an electrical capacitive storage and periodic switching mechanism. The switched capacitor acts as an energy storage element that replaces the need for continuously active biasing circuitry, thereby maintaining signal quality through proper voltage levels while consuming significantly less power.
4Manufacturing precision
If switched capacitor circuit updates bias voltage frequently, then linearity is improved, but bandwidth may be affected
Solution Approach 1:
The patent applies partial action by updating the bias voltage at specific phases rather than continuously. The switched capacitor circuit updates the bias voltage at the optimal rate - fast enough to maintain linearity during signal processing but not so fast as to create bandwidth limitations. This partial updating approach provides sufficient bias stability for linear operation without excessively limiting the signal bandwidth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides the desired linearity for discrete-time signal processing without sacrificing bandwidth or power consumption, with reduced power dissipation compared to conventional active devices, suitable for applications like chip-to-chip interconnects and data center routers.
Implementation Method 1
a capacitive element coupled to respective gate terminals of the at least two transistors, and configured to provide a DC signal to the respective gate terminals
Implementation Method 2
a switch configured to couple the capacitive element to a DC reference voltage in a second time period
Data Source
AI summary
A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.