Switched Capacitor Circuit With Parasitic Linearity Compensation

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Solution Overview

Problem

Prior art switched capacitors exhibit nonlinearity in their equivalent capacitance due to parasitic capacitors, which is undesirable in many applications.

Innovation Solution

A switched capacitor circuit design incorporating N-type and P-type switches, transmission gates, and capacitors, where the switches and transmission gates are controlled by complementary signals to maintain linearity in both states, and the use of PMOS and NMOS transistors to offset nonlinearities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a prior art switched capacitor uses an NMOS transistor as a switch, then it can provide DC coupling between nodes, but parasitic capacitors are introduced that cause nonlinearity in the equivalent capacitance

Engineering Contradiction:
ImproveDC coupling capabilityVSAvoidlinearity of equivalent capacitance
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent introduces parasitic capacitors in a controlled manner through additional switches and transmission gates, converting the harmful effect of unwanted parasitic capacitance into a beneficial design feature. By deliberately adding these parasitic capacitors with specific values, the circuit achieves linear equivalent capacitance in both switched states, thereby solving the nonlinearity problem caused by inherent transistor parasitic capacitance

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Adaptability or versatility

If the switched capacitor is designed to have different capacitance values in different states, then it provides switching functionality, but the parasitic capacitors make the capacitance nonlinear and unpredictable

Engineering Contradiction:
Improveswitching between capacitance statesVSAvoidlinearity of equivalent capacitance
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent changes the parameters of parasitic capacitors (their values and configurations) to achieve the desired effect. By carefully selecting the values of additional parasitic capacitors and configuring them in specific arrangements, the circuit maintains linear equivalent capacitance across different switching states, enabling predictable capacitance switching while preserving linearity

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If additional components are added to offset nonlinearities, then linearity is improved, but device complexity increases

Engineering Contradiction:
Improvelinearity of equivalent capacitanceVSAvoidnumber of switches and capacitors
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The additional switches and transmission gates in the patent serve multiple functions simultaneously: they provide the necessary DC coupling paths, introduce controlled parasitic capacitance to counteract nonlinearity, and enable the circuit to achieve linear operation in both switched states. This multi-functionality reduces the relative complexity by making each component work toward multiple objectives

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10560074B1Switched capacitor circuit and method thereof
Publication Date: 2020.02.11 REALTEK SEMICON CORP
  • US10560074B1 patent drawing
  • US10560074B1 patent drawing
  • US10560074B1 patent drawing

AI summary

A method couples a first bias signal to first and second internal nodes via first and second resistors, couples a second bias signal to third and fourth internal nodes via third and fourth resistors, couples the first internal node to the second internal node via a switch of a first type, and couples the third internal node to the fourth internal node via a switch of a second type. The method further couples the first internal node to the third internal node via a first transmission gate, couples the second internal node to the fourth internal node via a second transmission gate, couples a first terminal to the first and third internal nodes via first and third capacitors, respectively, and couples a second terminal to the second and fourth internal nodes via second and fourth capacitors, respectively.