Switched-Capacitor Differential Amplifier for Low-Voltage Gain
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Solution Overview
Problem
Differential amplifiers with diode-connected loads face challenges at low supply voltages, where transistors operate in the linear region, reducing gain, and require more stages to achieve desired gain, increasing area and current consumption.
Innovation Solution
A differential amplifier design that includes a pair of input transistors and load transistors, with at least one capacitor switchably coupled to a bias voltage source during specific phases, allowing for improved gain and reduced supply voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If diode-connected loads are used in differential amplifier, then the amplifier can be implemented without explicit common-mode feedback circuitry and provides gain of 15 to 20 dB per stage, but at low supply voltages the transistors operate in the linear region which reduces the gain
Solution Approach 1:
The patent applies dynamic biasing by switching the load transistors between diode-connected configuration (during auto-zero phase) and linear region operation (during signal amplification phase). This dynamic reconfiguration allows the circuit to adapt to different operational requirements, maintaining high gain while enabling low supply voltage operation.
Solution Approach 2:
The patent changes the operating parameters of the load transistors by controlling their connection configuration. During auto-zero phase, they are connected in diode configuration to provide high impedance; during signal phase, they operate in linear region with controlled impedance, thereby optimizing gain and enabling low-voltage operation.
2Temperature
If resistive load is used in differential amplifier, then the amplifier can operate at low supply voltages, but the gain is limited by the dc voltage drop across the resistors requiring more cascaded stages
Solution Approach 1:
The patent uses periodic switching between different load configurations. During auto-zero phase, diode-connected loads provide high impedance for offset cancellation; during signal phase, the switching action allows recovery of voltage headroom, effectively providing periodic optimization of both gain and voltage operation.
Solution Approach 2:
The switching network acts as an intermediary that dynamically reconfigures the load transistors. This intermediary element enables the circuit to switch between diode-connected and linear operation modes, mediating between the conflicting requirements of high gain and low supply voltage operation.
3Reliability
If more cascaded stages are used to achieve desired gain with resistive load, then the gain requirement is met, but the area and current consumption increase
Solution Approach 1:
By dynamically reconfiguring the load transistors between diode-connected and linear operation modes, the patent achieves high gain in a single stage rather than requiring multiple cascaded stages. This dynamic operation reduces the overall circuit area while maintaining the required gain performance.
Solution Approach 2:
The auto-zero phase performs preliminary offset cancellation by storing the offset voltage on capacitors before the signal amplification phase. This preliminary action eliminates the need for additional correction stages, reducing the total number of stages required and thereby reducing area and current consumption.
Data Source
AI summary
A differential amplifier includes a differential input, and a differential output. The differential amplifier further includes at least one capacitor switchably coupled to at least one bias voltage source during a first phase. The differential amplifier further includes a pair of input transistors having an input-transistor-first-terminal coupled to a first supply node, an input-transistor-second-terminal coupled to a respective one output of the differential output, and an input-transistor-control-terminal switchably coupled to (i) a second supply node during a second phase and (ii) a respective one input of the differential input during a third phase. The differential amplifier includes a pair of load transistors having a load-transistor-first-terminal coupled to a respective one output of the differential output, a load-transistor-second-terminal coupled to the second supply node, and a load-transistor-control-terminal. The at least one capacitor is switchably coupled between the load-transistor-first-terminal and the load-transistor-control-terminal during the second phase and the third phase.