Switched-Capacitor MDAC Architecture for Multi-Bit Pipelined ADCs
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Solution Overview
Problem
Designing multiplying digital-to-analog converters (MDACs) for pipelined analog-to-digital converters (ADCs) is challenging due to requirements for high linearity, low noise, and efficient power consumption, especially in achieving multi-bit stages without being constrained to 1-bit effective stages.
Innovation Solution
The implementation of a switched capacitor MDAC using charge redistribution and open loop charge pump gain circuitry, which decouples common modes and allows for higher precision without the need for level shifters, thereby simplifying the circuit architecture and improving noise gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional MDAC implementations are used, then multi-bit stages can be achieved, but the circuit complexity increases and precision is limited due to noise and level shifter requirements
Solution Approach 1:
The patent extracts and removes the level shifter component from the MDAC circuit architecture. By eliminating the level shifter, the circuit complexity is reduced while maintaining precision through the switched capacitor architecture that inherently handles voltage levels through charge redistribution rather than requiring active level shifting circuits.
Solution Approach 2:
The patent replaces traditional voltage-based amplification and level shifting mechanisms with charge-based switched capacitor mechanisms. This substitution uses charge redistribution across capacitors during different phases to achieve both amplification and level adaptation, eliminating the need for separate level shifter circuits and reducing overall complexity while improving precision.
2Power
If conventional charge pump gain circuitry is used, then amplification is achieved, but noise increases and power consumption rises
Solution Approach 1:
The patent employs periodic switching of capacitor connections between different phases (sampling phase, holding phase, amplification phase). During the amplification phase, capacitors are connected to provide gain, while during other phases they are disconnected or reconfigured. This periodic action enables amplification only when needed, reducing continuous power consumption and minimizing noise generation compared to conventional continuous charge pump circuits.
Solution Approach 2:
The switched capacitor circuit uses the input signal itself and reference voltages to charge and discharge capacitors, which then automatically provide the required amplification through charge redistribution. The circuit serves its own amplification needs through passive charge sharing between capacitors rather than requiring active charge pump transistors that consume power and generate noise.
3Measurement precision
If 1-bit effective stages are used, then circuit simplicity is maintained, but precision is constrained and multi-bit performance cannot be achieved
Solution Approach 1:
The patent implements dynamic switching of capacitor connections that can be configured for different operating modes. The same switched capacitor circuit can operate as a 1-bit stage or be configured for multi-bit operation by changing the switching patterns and capacitor connections. This dynamic reconfigurability allows the circuit to adapt to different precision requirements without sacrificing circuit simplicity, enabling multi-bit performance when needed while maintaining the ability to operate in simpler 1-bit mode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of linear DACs without the constraints of 1-bit stages, improving precision and reducing noise and complexity, while allowing for easier implementation of multi-bit per stage pipelined architectures.
Implementation Method 1
A first charge pump gain circuit comprising a first capacitor having a top plate to receive a first complementary analog input signal and a bottom plate to output a first complementary output, a second capacitor having a top plate to receive a second complementary analog input signal and a bottom plate to receive a first complementary reference voltage, and a first transfer switch for summing charges on the first and second capacitors
Data Source
AI summary
Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.