Switched Capacitor Multiplier for In-Memory Neural Network Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Machine learning applications face challenges in executing arithmetic operations efficiently due to high energy costs and latency associated with digital circuits, especially in deep neural networks, which can be mitigated by employing analog circuits for neural network computations.
Innovation Solution
A switched capacitor-based multiplication architecture that operates within four clock phases, eliminating the need for a dedicated digital-to-analog converter and reducing latency, energy consumption, and component count, while maintaining high signal quality and signal-to-noise ratio, by using capacitors and switches to perform neural network computations proximate to memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If arithmetic operations are executed using digital circuits, then computation accuracy is maintained, but energy consumption increases and latency is introduced
Solution Approach 1:
The patent replaces digital circuit-based arithmetic operations with analog circuit-based operations. Specifically, it uses a switched capacitor multiplier circuit that performs multiplication through analog voltage and capacitor charge relationships, eliminating the need for traditional digital arithmetic logic units. This substitution dramatically reduces energy consumption while maintaining sufficient computation accuracy for machine learning applications.
Solution Approach 2:
The patent changes the fundamental parameter of computation from digital binary states to analog voltage levels and capacitor charges. By using capacitor voltage relationships to represent and compute numerical values, the system operates in the analog domain where energy consumption is significantly lower compared to digital switching operations, while still achieving acceptable precision for neural network computations.
2Loss of time
If arithmetic operations are executed proximate to memory, then latency and data transfer overhead are reduced, but device complexity increases
Solution Approach 1:
The patent merges the computation function directly into the memory structure by integrating the switched capacitor multiplier circuit with the memory array. The capacitors used for computation are the same or closely coupled with the memory storage elements, eliminating the need for separate computation units and reducing the distance data must travel between storage and processing, thereby reducing latency without proportionally increasing complexity.
Solution Approach 2:
The patent makes the memory structure multi-functional by enabling it to perform both storage and computation operations. The same capacitor array that stores data can be reconfigured through the switched capacitor circuit to perform multiplication operations, allowing the memory device to serve dual purposes and reducing the need for additional dedicated computation hardware.
3Device complexity
If dedicated digital-to-analog converters are eliminated, then device complexity and component count are reduced, but signal quality may deteriorate
Solution Approach 1:
The patent extracts and removes the dedicated digital-to-analog converter component from the system architecture. Instead of converting digital signals to analog through a separate DAC unit, the system directly uses analog voltage levels and capacitor charge states to represent and process data throughout the computation pipeline, eliminating the DAC component entirely while maintaining signal quality through careful analog circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low latency, reduced energy consumption, and increased efficiency in executing neural network computations, enabling effective classification accuracy with low-precision computations and minimizing data transfer overhead by performing operations in-memory.
Implementation Method 1
A switched capacitor-based multiplication architecture that operates within four clock phases
Implementation Method 2
using capacitors and switches to perform neural network computations proximate to memory
Data Source
AI summary
Systems, apparatuses and methods include technology that identifies whether a product of first and second digital numbers is associated with a positive value or a negative value. During a first clock phase, the technology sets a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value. During the first clock phase, the technology controls switches to supply the first reference voltage to first plates of capacitors. Each of the capacitors includes a respective first plate of the first plates and a second plate. Further, during the first clock phase, the technology controls the switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.